Skip to content
View disco0's full-sized avatar

Block or report disco0

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Content in all repositories owned by your account will be closed.
Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Starred repositories

2 stars written in Verilog
Clear filter

FPGA implementation of DEC PDP-1 computer (1959) in Verilog, with CRT, Teletype and Console.

Verilog 195 18 Updated Jul 9, 2022

FPGA based MIT CADR lisp machine - rewritten in modern verilog - boots and runs

Verilog 166 16 Updated Jan 2, 2016