Personal Verilog solutions and study notes created while working through HDLBits.
Verilog Language/— language fundamentals, vectors, procedures, and module hierarchyCircuits/Combinational Logic/— combinational circuit exercisesCircuits/Sequential Logic/— sequential circuit exercisesNOTES.md— detailed Korean study notes and selected solution explanations
Each exercise is kept as a small standalone HDL source file so that individual topics can be reviewed independently. This repository is a learning archive rather than a reusable RTL library.
Problem statements belong to HDLBits; the solution code and notes in this repository are the author's own study work.