JS_NTT

Configurable Number Theoretic Transform (NTT/INTT) hardware accelerator for lattice-based post-quantum cryptography.

The RTL shares arithmetic and butterfly resources across several parameter sets and transform structures:

• Dilithium/ML-DSA and Kyber/ML-KEM radix-2 transforms
• HAETAE arithmetic
• NTRU+ parameter sets with radix-2 and radix-3 paths
• Cooley–Tukey forward and Gentleman–Sande inverse butterflies
• Banked BRAM interfaces and external twiddle-factor ROM interfaces

Install Icarus Verilog (iverilog and vvp), then run:

make -C tool_sim

Useful targets:

make -C tool_sim dili_only  # short Dilithium forward-NTT check
make -C tool_sim timing     # one-vector timing-focused run
make -C tool_sim full       # broader configured test set

The SystemVerilog testbench compares RTL results with in-testbench software reference calculations and reports PASS, FAIL, and first write-back timing.

• rtl_verilog/ — top-level NTT controller, unified butterfly, modular multipliers, and shared headers
• sim_verilog/ — SystemVerilog testbenches and twiddle tables
• sim_verilog/python/ — Python reference models for radix-2 and radix-3 transforms
• tool_sim/ — reproducible Icarus Verilog commands

This repository contains research RTL and simulation material. Integrators should verify the selected parameters, arithmetic domain, timing constraints, and target-device results before deployment.