Skip to content
View dobios's full-sized avatar
☃️
Wishing for snow
☃️
Wishing for snow

Organizations

@llvm @chipsalliance @chiselverify @GameLab-UNIL-EPFL

Block or report dobios

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results

Animated sprite editor & pixel art tool (Windows, macOS, Linux)

C++ 37,485 8,155 Updated Jun 12, 2026
Scala 27 23 Updated Dec 4, 2025

Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.

C++ 1,416 99 Updated Jun 5, 2026

Agile Hardware Design Course

Scala 15 7 Updated Nov 17, 2025
Python 5 Updated Jun 11, 2026
Makefile 4 Updated Jun 12, 2026

LLM-Assisted Hardware Formal Verification Tool

Rust 108 24 Updated Jun 10, 2026
Python 33 5 Updated Nov 2, 2025

design and verification of asynchronous circuits

Python 51 Updated Apr 26, 2026

The Task Parallel System Composer (TaPaSCo)

Verilog 126 29 Updated Jun 9, 2026
TeX 3 1 Updated May 29, 2026

Bluespec Compiler (BSC)

Haskell 1,118 180 Updated Jun 11, 2026

Formal specification and verification of hardware, especially for security and privacy.

Coq 133 20 Updated May 19, 2022

Circuit IR Compilers and Tools with memory support

C++ 1 Updated Jun 8, 2026

Rust bindings for CIRCT

Rust 17 1 Updated Apr 20, 2024

Perfect Green Screen Keys

Python 13,867 857 Updated May 28, 2026
Scala 1 Updated Feb 10, 2026

Pony is an open-source, actor-model, capabilities-secure, high performance programming language

Pony 6,127 435 Updated Jun 14, 2026

An experiment in hardware accelerated DSLs and parallel algorithms for signal processing applications.

Rust 10 Updated Oct 22, 2025

High level synthesis language for hardware design

C++ 97 10 Updated Jun 10, 2026

Yosys Open SYnthesis Suite

C++ 4,531 1,097 Updated Jun 12, 2026

Haskell to VHDL/Verilog/SystemVerilog compiler

Haskell 1,599 166 Updated Jun 12, 2026

A Hardware Description Language based on the Rust Programming Language

Verilog 311 25 Updated Apr 21, 2026

Collection of larger-scale tests for CIRCT.

SystemVerilog 9 2 Updated Jun 14, 2026

WIP

Python 1 Updated Oct 8, 2025

Lark is a parsing toolkit for Python, built with a focus on ergonomics, performance and modularity.

Python 5,909 484 Updated Jun 7, 2026

Nagini is a static verifier for Python 3, based on the Viper verification infrastructure.

Python 283 14 Updated Jun 13, 2026

A collection of datapath circuit design and verification benchmarks

SMT 19 Updated Feb 10, 2026

SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows

Python 519 94 Updated Jun 9, 2026
Next