Yosys Open SYnthesis Suite

Haskell to VHDL/Verilog/SystemVerilog compiler

A Hardware Description Language based on the Rust Programming Language

Collection of larger-scale tests for CIRCT.

WIP

Lark is a parsing toolkit for Python, built with a focus on ergonomics, performance and modularity.

Nagini is a static verifier for Python 3, based on the Viper verification infrastructure.

A collection of datapath circuit design and verification benchmarks

SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows

A core language for rule-based hardware design 🦑

Safe Interactions with Foreign Languages through Omniglot

A Python compiler design toolkit.

Repository for the sustainable development tycoon game, being developped under the SURE project.

A Platform for High-Level Parametric Hardware Specification and its Modular Verification

Most influential papers in programming languages

End-to-end synthesis and P&R toolchain

[MIRROR, PRs ok! Issues: https://git.lix.systems/lix-project/lix/issues] A modern, delicious implementation of the Nix package manager, focused on correctness, usability, and growth — and committed…

Application that simulates a large grid of Pokémon types fighting each other.

An experimental hardware compiler

Incremental Model Checking Toolkit

The rustic MLIR bindings in Rust

Rust bindings for Godot 4

Graph data structure library for Rust.

Graph library for Rust

Package circt using nix + flakes

chomp

PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g., Verilog, SystemVerilog)

Women in Programming Languages and Software Engineering Research

mGBA Game Boy Advance Emulator

Egraphs Modulo Theories