UVM 1.2 port to Python

The UVM written in Python

Contains the code examples from The UVM Primer Book sorted by chapters.

PCIE 5.0 Graduation project (Verification Team)

Python - 100天从新手到大师

DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision

🌈Python3网络爬虫实战：淘宝、京东、网易云、B站、12306、抖音、笔趣阁、漫画小说下载、音乐电影下载等

A collection of design patterns/idioms in Python

python爬虫教程系列、从0到1学习python爬虫，包括浏览器抓包，手机APP抓包，如 fiddler、mitmproxy，各种爬虫涉及的模块的使用，如：requests、beautifulSoup、selenium、appium、scrapy等，以及IP代理，验证码识别，Mysql，MongoDB数据库的python使用，多线程多进程爬虫的使用，css 爬虫加密逆向破解，JS爬虫逆向，…

《笨方法学 Python》（Learn Python the Hard Way）学习笔记

Python3编写的各种大小程序，包含从零学Python系列、12306抢票、省市区地址库以及系列网站爬虫等学习源码

My Python Examples

喜欢的技术书籍

riscv-debug-spec的中文文档

The Python programming language

Final Project for my course in Advanced Verification with SystemVerilog OOP

Verification of a 10 Gigabit Ethernet MAC using a SystemVerilog OOP Testbench

Ethernet-MAC System verilog

A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM

This is the repository for the IEEE version of the book

This is the main repository for all the examples for the book Practical UVM

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翻墙-科学上网

Community managed domain list

Awesome ASIC design verification

AHB to APB Bridge VIP

Parameterised Asynchronous AHB3-Lite to APB4 Bridge.

Verilog AXI components for FPGA implementation

Must-have verilog systemverilog modules

IC design and development should be faster，simpler and more reliable