My Python Examples

Python - 100天从新手到大师

Python3编写的各种大小程序，包含从零学Python系列、12306抢票、省市区地址库以及系列网站爬虫等学习源码

Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.

OpenTitan: Open source silicon root of trust

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

fifo verification IP using system verilog

Functional verification project for the CORE-V family of RISC-V cores.

This repository contains a Verification IP for the timer. This VIP tests the timer by applying constrained random stimulus. Sequences of transactions reset, configure the timer, and perform read & …

Development UVM Verification Environment for ALU DUT

IC design and development should be faster，simpler and more reliable

Verilog AXI components for FPGA implementation

RISC-V Formal Verification Framework

IC Verification & SV Demo

Verification IP for I2C protocol

RISC-V CPU Core (RV32IM)

SystemVerilog UVM testbench example

An Open-Source Design and Verification Environment for RISC-V

UVM code to verify ALU

An uvm verification env for ahb2apb bridge

System on Chip verified with UVM/OSVVM/FV

MPSoC verified with UVM/OSVVM/FV

A simple, basic, formally verified UART controller

For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug

Verification IP for APB protocol

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

UVM Verification IP to uart2bus IP.

Verification IP for APB protocol