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51 results for source starred repositories written in Verilog
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SERV - The SErial RISC-V CPU

Verilog 1,666 231 Updated Oct 17, 2025

An open source GPU based off of the AMD Southern Islands ISA.

Verilog 1,250 254 Updated Aug 18, 2025

MNT VA2000, an Open Source Amiga 2/3/4000 Graphics Card (Zorro II/III), written in Verilog

Verilog 1,010 79 Updated Dec 15, 2022

3-stage RV32IMACZb* processor with debug

Verilog 949 69 Updated Oct 28, 2025

Project Apicula 🐝: bitstream documentation for Gowin FPGAs

Verilog 594 79 Updated Oct 28, 2025

An open source SPI flash emulator and monitor

Verilog 384 44 Updated Jul 17, 2020

A Verilog implementation of DisplayPort protocol for FPGAs

Verilog 260 57 Updated Mar 15, 2019

Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)

Verilog 257 49 Updated Aug 21, 2023

A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals

Verilog 245 32 Updated Nov 29, 2018

The Easy 8-bit Processor

Verilog 184 20 Updated Jun 9, 2014

Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs

Verilog 182 18 Updated Mar 10, 2024

An open source FPGA design for DSLogic

Verilog 168 80 Updated Jul 8, 2014

Compact FPGA game console

Verilog 165 14 Updated Nov 14, 2023

Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.

Verilog 155 19 Updated Jun 24, 2021

IceChips is a library of all common discrete logic devices in Verilog

Verilog 148 24 Updated Oct 2, 2025

Imitate SDcard using FPGAs. 使用FPGA模拟伪装SD卡。

Verilog 129 26 Updated Sep 14, 2023

64x64 LED Cube based on the Colorlight 5a-75B LED driver board.

Verilog 104 16 Updated Jan 11, 2023

FPGA based transmitter

Verilog 99 15 Updated Apr 14, 2017

Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks

Verilog 91 18 Updated Jul 3, 2019

FPGA Odysseus with ULX3S

Verilog 68 12 Updated Nov 1, 2023

TCP/IP controlled VPI JTAG Interface.

Verilog 67 47 Updated Jan 16, 2025

Source code to accompany https://timetoexplore.net

Verilog 63 25 Updated Aug 25, 2020

ice40 USB Analyzer

Verilog 57 8 Updated Aug 8, 2020

The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the FPGA can be monitored in a waveform.

Verilog 56 5 Updated Sep 24, 2025

Minimig for the DE1 board

Verilog 49 20 Updated Apr 18, 2022

FPGA Tools and Library

Verilog 46 2 Updated May 1, 2023

Code to support porting MiST cores to other boards.

Verilog 46 16 Updated Apr 19, 2025

This repository contains software for BeagleWire. It is a realization of my project for GSOC-2017

Verilog 46 16 Updated Oct 10, 2018

The OpenCores aoOCS SoC is a Wishbone compatible implementation of most of the Amiga Original Chip Set (OCS) and computer functionality. aoOCS is not related in any way with Minimig - it is a new a…

Verilog 41 9 Updated Mar 29, 2014

RetroCade Synth - C64 SID, YM2149, and POKEY audio chips with MIDI interface.

Verilog 38 19 Updated Jan 5, 2017
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