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4 stars written in SystemVerilog
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Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

SystemVerilog 1,705 672 Updated Dec 19, 2025

Proving leftpad correct two-dozen different ways

SystemVerilog 714 65 Updated Apr 21, 2025

Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.

SystemVerilog 317 91 Updated Dec 19, 2025

Ocelot: The Berkeley Out-of-Order Machine With V-EXT support

SystemVerilog 205 29 Updated Dec 15, 2025