A little project to provide the fpga design for a PCIe inteface running on the LiteFury development board.

Verilog and ARM Assembly labs for second year Digital and Computer Systems (ECE253) course at the University of Toronto

Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀

This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our goal is to help both beginners and experienced users understa…

If you live in the terminal, kitty is made for you! Cross-platform, fast, feature-rich, GPU based.

An arctic, north-bluish clean and elegant tmux color theme.

A simple guide (and example of configuration) about how to install i3 & its and essentials packages, then make them look eye candy, also contains my dotfiles of Debian 12 (Bookworm) setup

A huge collection of Rofi based custom Applets, Launchers & Powermenus.

🤘 The biggest collection of themes for Terminator terminal.

Active fork of kien/ctrlp.vim—Fuzzy file, buffer, mru, tag, etc finder.

🍿 A collection of QoL plugins for Neovim

Starter template for LazyVim

RISC-V by VectorBlox

8051/8052 emulator with curses-based UI

Lightweight 8051 compatible CPU

A RISC-V emulator for the 8051 (MCS-51) microcontroller.

uvm AXI BFM(bus functional model)

AXI3 Bus Functional Models (Initiator & Target)

Wishbone Bus Functional Model

A simple simulator for the 8051 microcontroller

Yet another free 8051 FPGA core

8051 core

Software emulator for an 8051 microprocessor. using a 8051 microprocessor

RV3N--- a RV32IMC processor core, which has a new pipeline with "3+N" stages.

8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.

Animated pipes terminal screensaver

Generic AXI master stub

FTDI FT600 SuperSpeed USB3.0 to AXI bus master

SDRAM controller with AXI4 interface