Skip to content
View fifteenhex's full-sized avatar
🧟‍♂️
No more strong zeros
🧟‍♂️
No more strong zeros
  • The inaka, Japan

Organizations

@thingyjp @breadbee @linux-chenxing

Block or report fifteenhex

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
4 stars written in Assembly
Clear filter

A FPGA friendly 32 bit RISC-V CPU implementation

Assembly 2,907 470 Updated Oct 20, 2025

Legacy: TTL-only CPU featuring UART I/O, an expansion port, 512KB SSD at up to 10MHz clock speed

Assembly 175 30 Updated Jul 18, 2025

A RISC-V emulator for the 8051 (MCS-51) microcontroller.

Assembly 145 8 Updated Sep 3, 2024

Reimplementation of WarpOS supporting Sonnet Crescendo 7200 and other PowerPC PCI cards (mirror of CVS development repository).

Assembly 43 4 Updated Dec 19, 2020