Skip to content
View fifteenhex's full-sized avatar
🧟‍♂️
No more strong zeros
🧟‍♂️
No more strong zeros
  • The inaka, Japan

Organizations

@thingyjp @breadbee @linux-chenxing

Block or report fifteenhex

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
11 stars written in Verilog
Clear filter

SERV - The SErial RISC-V CPU

Verilog 1,666 231 Updated Oct 17, 2025

A tiny Open POWER ISA softcore written in VHDL 2008

Verilog 698 108 Updated Oct 9, 2025

Project Apicula 🐝: bitstream documentation for Gowin FPGAs

Verilog 594 79 Updated Oct 28, 2025

iCESugar FPGA Board (base on iCE40UP5k)

Verilog 404 106 Updated Sep 16, 2025

An open source SPI flash emulator and monitor

Verilog 384 44 Updated Jul 17, 2020

iCESugar-nano FPGA board (base on iCE40LP1K)

Verilog 134 22 Updated Sep 16, 2025

FPGA core boards / evaluation boards based on CDCTL hardware

Verilog 93 41 Updated Sep 9, 2021

Memory system and UART implemented on Tang Nano 20K for DEC DCJ11 PDP-11 Processor

Verilog 76 4 Updated Sep 29, 2025

Basic loadout for SQRL Acorn CLE 215/215+ board. Blinks all LEDs, outputs square waves on all 12 GPIO outputs

Verilog 69 8 Updated Nov 21, 2021

Motorola 68000 (32 bit with unneeded instructions removed) in an FPGA.

Verilog 16 1 Updated Mar 24, 2024

A general purpose computer platform for retrocomputing enthusiasts

Verilog 8 2 Updated Mar 21, 2025