Tags: fontamsoc/ftpu

ftpu.20260807

* gcc 007d5ccd6b7...6141667e2de (1):
  > RISC-V: never use the GPR save/restore millicode

* newlib a1540caea...a010650a1 (2):
  > hwdrvirqctrl.h: place every command and result index at word bit 3
  > hwdrvirqctrl.h: fix agreement in the command descriptions

* hw 6d4f63c...20be5b1 (45):
  > rv32-sim/apps: rebuild binaries
  > rv32-orangecrab0285: rebuild bitstream and logs
  > cpu/README: name the processing unit FonTamPU
  > rename rvxx -> ftpu
  > rename rvxx/cpu.sv -> cpu/ccx.sv
  > rvxx/README: note the load and store func3 encodings that do not trap
  > rv32-sim/apps/tailchain: include a copy of hwdrvirqctrl.h
  > dev/irqctrl: place every command and result index at word bit 3
  > rv32-sim/apps/isatests: reword why rv32si/wfi and illegal are excluded
  > rv32-sim/gtkw/mie: drop the software-interrupt rows
  > rvxx/README: record that software interrupts are not implemented
  > rvxx/sys: remove Machine and Supervisor Software Interrupt support
  > lib/xc7pll_100_to_48_96_192: hold pll1 in reset until pll0 locks
  > lib/xc7pll: name the pll ports after the frequency they carry
  > rv32-orangecrab0285: replace ecp5pll with a pre-generated pll
  > rv32-sim/apps/coremark: end the run with a ---- separator
  > rvxx: add PUDCACHEREGRESP, registering the dcache response path
  > rename rsp->resp
  > rvxx/pu: default IMULCNT and IDIVCNT to 1
  > rvxx/README: document the bus grant fairness bound
  > lib/wb_arbiter: report a grant held past the fairness bound
  > rv32-sim/apps/smplock: drop the pacing from its cross-hart wait
  > rv32-sim/apps/smpfair: test that a stalled master cannot starve the others
  > lib/wb_arbiter: bound how long a master can hold the bus grant
  > rvxx/dcache: size the coherency ring skidbuf to its payload
  > dev/sram: default SIZE to the documented minimum of 2
  > dev/irqctrl: comment out the unused wb_addr_i port
  > rvxx/README: document the coherency write barrier
  > rvxx/dcache: report a coherency write pending count that overflows
  > rvxx/dcache: size the coherency write pending counter to the ring capacity
  > rvxx/README: document the bus lock contract
  > lib/wb_arbiter: report a bus lock held long enough to have starved the others
  > rv32-sim/apps/smplock: test that an atomic sequence cannot starve a hart
  > wishbone: release the bus lock on the lock owner's next unlocked access
  > rv32-sim/apps/isatests: enable the lrsc wrong-reservation test case
  > rvxx/lsu: fail a store-conditional whose address is not the reserved one
  > rvxx/icache: do not believe a hit read while the cache reset was writing
  > rvxx/README: note that the alternate link register is not supported
  > rvxx/README: describe the return-address-stack semantics
  > rvxx/pu: document why the return-address-stack underflow keeps ras7
  > rvxx/idiv: fold the multiply operand select into the operand capture
  > rv32-sim/apps/isatests: add a csr write-select test
  > rvxx/imul: fold the sign extension into the operand capture
  > rvxx/README: correct what rdWasLocked is consulted for
  > rvxx/pu: keep rdWasLocked set when the unlock is suppressed

rvpu.20260726

* gcc 0b22da6625a...a0aa5bde303 (2):
  > RISC-V: Add -mfused-madd to disable R4-type FMA instruction patterns
  > make -mbranch-cost= default value 2

* newlib 305f72aa3...8e7ee19ed (23):
  > underLineOS: retarget gdbstub config symbols with --defsym
  > underLineOS: gdbstub debugs the thread selected through __gdbstub_tp
  > underLineOS: clear mscratch when __switchctx() idles a CPU
  > ran autoreconf2.69 in libgloss/
  > underLineOS: gdb remote-serial-protocol stub in its own libgdbstub.a
  > underLineOS: build libgloss with -march=rv32ima_zicsr_zifencei
  > underLineOS: load the interrupt-cause msb with a single li
  > underLineOS: gate trap tail-chaining behind USETAILCHAIN
  > underLineOS: tail-chain pending interrupts at trap return
  > ran autoreconf2.69 in libgloss/
  > underLineOS: drop __thread_schedoncpu() by never moving a running thread
  > underLineOS: access atomically-manipulated variables only with atomics
  > underLineOS: park harts for which there are no per-CPU data
  > underLineOS: pad _savedctx_t to a multiple of 16 bytes
  > underLineOS: fix _TIMER_DEF() using the _timer struct tag as a type
  > underLineOS: implement nanosleep() using _thread_sleep() and build it
  > underLineOS: compute _SECS() in 64bits
  > underLineOS: count in wq->p the threads about to wait, plainly accessed
  > underLineOS: make _mutex_lock() sleep again while timeout remains
  > underLineOS: always reprogram the timer compare value in _timer_arm()
  > underLineOS: handshake context saving before a thread can be resumed
  > underLineOS: do nothing waking up a thread that is already running
  > underLineOS: disarm the sleep _timer of a thread woken up early

* hw 9a5b3c9...6d4f63c (155):
  > rv32-sim/apps: rebuild binaries
  > rv32-orangecrab0285: rebuild bitstream and logs
  > rvxx/README: updates
  > rv32-orangecrab0285: restore use of lib/ecp5pll.sv
  > tools/serial_jtag: point the channel-top claims at the example branches
  > serial_jtag: align comments and README with the measured jtagg behavior
  > lib/serial_jtag_jtagg: register the tdo path on the delayed falling edge
  > lib/serial_jtag_phy: support the ecp5 JTAGG TAP through a pairing adapter
  > tools/serial_jtag: name the board sections in the README
  > lib/serial_jtag_phy: emit the device-to-host frame's first bit on time
  > lib/fifo: add a second synchronizer stage to the async gray-index crossings
  > rv32-nexysa7100: minimilize keeping possibilities commented-out
  > rv32-artya7100: minimilize keeping possibilities commented-out
  > rv32-orangecrab0285: minimilize keeping possibilities commented-out
  > rv32-sim: enable PUIDIVDSP PUFDIVDSP2 PUFSQRTDSP2
  > rv32-nexysa7100: route the SMP memory side through wb_cdc
  > rv32-orangecrab0285: route the SMP memory side through wb_cdc
  > rv32-artya7100: route the SMP memory side through wb_cdc
  > rvxx/idiv: fuse the PUIDIVDSPREG clz/normalize into one cascade
  > rvxx/pu: note when PUIDIVREGRQST is unnecessary
  > rvxx/idiv: add PUIDIVDSPREG, pipelining the NR DSP multiply
  > rvxx/dcache.pu: add PUAMOREGWB, registering the AMO write-back
  > rvxx/idiv: add PUIDIVREGRQST, registering the idiv request
  > rvxx/fpu: pipeline the NR fdiv/fsqrt multiplier (two column products)
  > rvxx/fpu: split the fcvt shift cones from their round/clamp stages
  > rvxx/fpu: pipeline the unpack/normalize front-end (stage U)
  > rvxx/imul: add PUIMULDSPREG, fully pipelining the DSP multiply
  > rvxx: add PUDCACHEREGRQST, registering the dcache request path
  > rv32-{arty,nexys}a7100: add 20 more implementation strategies runs
  > rv32-{arty,nexys}a7100: Use phys_opt AggressiveExplore (post route)
  > rv32-sim: instantiate serial_sim with `.POLLCYCLES (1024*8)`
  > rv32-*: instantiate cpu with `.USEMEMCLKDOM (!DCACHESZ)`
  > rv32-sim/coremark: retune EXTRA_CFLAGS (+1.54% CoreMark/MHz)
  > README: document the examples/* branches
  > README: list the tools directory
  > tools/serial_jtag: add the openocd console bridge
  > dev/serial_jtag: add serial console peripheral tunneled over jtag
  > lib/serial_jtag_fifo_phy: add async-fifo glue between wishbone clock and jtag tck
  > lib/serial_jtag_phy: add bscan user-dr engine for a byte-stream console
  > rv32-sim/apps/fputests: review makefile
  > rv32-sim/apps/fpusmoke: review makefile
  > rv32-sim/apps/divtest: review makefile
  > rv32-sim/apps/clmultest: review makefile
  > rv32-sim/apps/coremark: report CoreMark/MHz above CoreMark done
  > rv32-sim: reset-gate the invalid-address-space catcher
  > dev/serial_sim: don't emit a host byte during reset
  > rv32-sim: hold reset for at least 4 cycles
  > rvxx/icache: keep the fill way-select driven when WAYCNT == 1
  > rv32-sim/apps: gdbstubtest exercising libgdbstub.a
  > dev/serial_sim: NUL-terminate the pty path before reversing it
  > dev/serial_sim: add a pollcycles parameter throttling host reads
  > dev/irqctrl: report acknowledgement misses in simulation
  > rv32-sim/apps: tailchain test0, a blind acknowledge reports none pending
  > dev/irqctrl: acknowledge an interrupt only for its routed destination
  > rv32-sim/apps: enable tailchain test2, the interrupt-starvation repro
  > rvxx: keep a gated pending interrupt visible until it can trigger
  > rv32-sim/apps: add tailchain, testing _OS trap tail-chaining
  > rvxx/zbb: restructure the compute into op groups sharing one popcount and one comparator
  > rvxx/zbb: drop 37 flip-flops -- result reuses rs1Slot, optype decoded at iD
  > rvxx: restore Zbb as a multi-cycle unit (sim-on, FPGA-off)
  > dev serial_uart: raise the minimum supported baudrate from 110 to 1200
  > lib/xc7pll_100_to_48_96_192
  > lib/xc7pll_100_to_48
  > lib/xc7pll_48_to_48_96_192
  > lib/xc7pll_100_to_50_100_200: remove unused signals
  > rv32-sim/apps: add oststress, stress-testing _OS synchronization
  > dev+lib+rvxx+tops: fix comment typos across the codebase
  > lib/uart+dev serial_usb+rv32-sim: fix comment typos
  > dev irqctrl+serial_uart: document command-drop and CMDDEVRDY semantics
  > rvxx/pu: include sys.pu.sv after the rW_multicyclePending declaration it uses
  > rvxx/dcache: scope the max_pending stb note to newly-issued operations
  > rv32 xilinx tops: the build defines come from impl_1.sv, not a makefile
  > lib+dev serial_usb: PHYCLKFREQ must be 48 MHz -- fix the speed claims
  > dev/irqctrl: fix the IRQDSTCOUNT/IRQSRCCOUNT bound exponent
  > lib/uart+dev/serial_uart: correct baud examples, clock names, stop-bit and poweron notes
  > lib/fifo_fwft_async: fix synchronizer clocks -- clk_write_i/clk_read_i are not ports
  > lib/fifo: fix stale and copied port-doc claims across the fifo family
  > rvxx/idiv_seedgen: drop the dead initial r0 assignment
  > rvxx/imul+idiv: fix operand naming, PUIMULDSP notes, radix-2 wording
  > rvxx/fpu: drop stale staged-bring-up note, fix model refs and seed .vh headers
  > rvxx/dcache: fix the coherency dirty-state and max_pending comments
  > rvxx/sys: fix the documented interrupt priority order
  > rvxx/pu: fix stale parameter/port/decode comments
  > rvxx: fix stale pu.v/memctrl.pu.v filename references in comments
  > lib/wb_skidbuf: throttle on undelivered responses so the resp fifo cannot overflow
  > rv32-sim/apps/isatests: canonicalize -march, drop redundant -mabi
  > rv32-sim/apps/isatests: sync tests with upstream riscv-tests
  > rv32-sim/apps: merge isatests2 into isatests
  > rv32-sim/isatests: add x0fwd test for multicycle rd == x0 forwarding
  > rvxx/pu: do not forward a multicycle result retiring into x0
  > rvxx/pu: document feature defines in the header
  > rvxx/lsu: factor head-of-stream match into ldUnit_memAck_
  > rvxx/idiv: clarify division algorithm comments
  > rvxx/imul: clarify multiplication algorithm comments
  > Revert "rvxx/pu: decode isFcsrAccess at iF, register into iD_isFcsrAccess"
  > rvxx/pu: decode isFcsrAccess at iF, register into iD_isFcsrAccess
  > rvxx/pu: enable PURV32ZBC in all FPGA tops
  > rvxx/pu: document the WORDBITSZ/XWORDBITSZ parameters
  > rvxx/pu: document the MAXPENDINGACK parameter
  > rvxx/pu: doc the CLMULCNT/FPUCNT parameters, drop stale FADD/FMUL/FDIV counts
  > rv32-sim/coremark: add -fira-region=one -falign-functions=4
  > rvxx/idiv: multiply-based Newton-Raphson divider option -- PUIDIVDSP
  > rvxx/pu: single-cycle EX-stage clmul option -- PUCLMUL1
  > rv32 FPGA tops: refresh the PURV32ZBC comment (combinational clmul, measured FPGA-viable)
  > rvxx/clmul: make the combinational core the default, drop the iterative core + PUCLMULCOMB gate
  > rvxx/clmul: combinational (XOR-tree) clmul alternate -- PUCLMULCOMB
  > rvxx/fpu: DSP Newton-Raphson fsqrt -- faithful (PUFSQRTDSP) + correctly-rounded (PUFSQRTDSP2)
  > rvxx/fpu: DSP Newton-Raphson fdiv -- faithful (PUFDIVDSP) + correctly-rounded (PUFDIVDSP2)
  > rv32-sim/apps/isatests: misc makefile fix up
  > rv32 FPGA tops: document Zfinx as a commented-out option
  > rvxx/fpu: register the FP result/flags at op completion
  > rv32-sim/fpusmoke: comprehensive fmin/fmax/fsgnj/fclass coverage
  > rv32-sim/fputests: add feq/flt/fle to the TestFloat conformance set
  > rvxx/fpu: pipeline fcvt (shift / round-saturate split) (33 -> 34 MHz)
  > rvxx/fpu: split the shared packer (denormalize-shift / round) (31 -> 33 MHz)
  > rvxx/fpu: pipeline fadd/fsub front-end (25 -> 31 MHz)
  > rvxx/fpu: pipeline fmul + the shared packer back-end (15 -> 25 MHz)
  > rvxx/fpu: fix underflow flag on round-up-to-normal; full-coverage TestFloat
  > rvxx/fpu: Zfinx fdiv/fsqrt (iterative) -- FPU arithmetic complete
  > rvxx/fpu: Zfinx fadd/fsub/fmul (full IEEE-754)
  > rvxx/fpu: Zfinx fcvt (int<->float) + TestFloat conformance harness
  > rvxx/fpu: Zfinx single-precision FPU as a multi-cycle unit (1-cycle ops)
  > rvxx/pu: guard the multicycle iD_rW capture against a superseded late result
  > rv32-artya7100/nexysa7100: enable Zbs
  > rv32-orangecrab0285: enable Zbs
  > rvxx: add Zbs (bset/bclr/binv/bext + immediates), mirroring Zbb
  > rvxx: add Zbc (clmul/clmulh/clmulr) as a multi-cycle unit, modeled on idiv
  > rvxx: add Gshare branch prediction (PUPREDICTGSHARE, off by default)
  > Revert "rvxx/sys: factor the per-privilege IRQ-enable gate into shared wires"
  > rvxx/sys: factor the per-privilege IRQ-enable gate into shared wires
  > rvxx: precompute-then-select the next-PC, lifting Fmax off the fetch loop
  > rvxx: flatten constant-leg ternaries in the scoreboard ready/stall logic
  > rvxx: flatten iD_stalled operand-ready priority mux into per-operand needs
  > rvxx: keep gprLock off the gprUnlock timing cone
  > rvxx/lsu: compare LR/SC reservation against rs1, not the address adder
  > rv32-sim/apps: add divbench integer-divide latency microbenchmark
  > rvxx/idiv: radix-4 restoring division (halve divide latency)
  > Revert "rvxx/dcache: track occupancy with a dedicated up/down register"
  > rvxx/dcache: track occupancy with a dedicated up/down register
  > rvxx/memctrl: track occupancy with a dedicated up/down register
  > lib/wb_skidbuf: track occupancy with one up/down counter
  > rvxx: gate async traps precisely on a held load result
  > rvxx: give the pipeline WriteBack priority over multicycle units
  > lib/wb_skidbuf: also buffer the response path
  > rv32-*: feature-gate PURV32ZBB off for all FPGA tops
  > rvxx: reduce Zbb execute-stage area (one rotate shifter, clz via ctz)
  > rvxx: add support for Zbb extension
  > rvxx: add support for Zba extension (sh1add/sh2add/sh3add)
  > rvxx: drop redundant excTriggered from eX_JumpOrBranch_i inner AND
  > rvxx: dedicated branch comparator off the shared subtract
  > remove reliance on FPGA power-on init values
  > dev/gpio: remove wrong comment
  > rv32-sim: makefile improvements
  > lib/wb_mux: enable ADDRSPACE_SEQINIT by default
  > fix %Warning-MULTIDRIVEN

rvpu.20260611

* newlib b1f42d552...10edf8648 (10):
  > underLineOS: bugfix: enable interrupt delivery to core0
  > underLineOS: improve _thread_sched()
  > underLineOS: _thread_schedoncpu(): _oops() if runq->cnt invalid
  > underLineOS: fix _thread_schedoncpu() to run thread asap
  > underLineOS: improve __thread_wakeup()
  > underLineOS: bugfix how _waitq_t.p gets used
  > underLineOS: bugfix thread scheduling
  > underLineOS: improve _thread_schedoncpu() _thread_stop()
  > underLineOS: macros rework

* hw 04b51d8...9a5b3c9 (15):
  > rv32-sim/apps: rebuild binaries
  > rv32-orangecrab0285: rebuild bitstream and logs
  > rv32-sim/apps/thrdtst: outputs adjustments
  > rv32-sim/apps/tinyraytracer: output result in its own line
  > rv32-sim/apps/thrdtst: test semaphore timeout
  > rv32-sim: gtkwave translate filter files
  > lib/core_usb_*: remove async reset
  > Review rst_i usage
  > rename lib/rstbtnctrl.sv -> lib/rstctrl.sv
  > /dev/gpio: remove combinational logic on wb_dat_o
  > /dev/gpio: misc improvements
  > lib/wb_mux: add option to initialize `addrspace` sequentially
  > dev/sram: remove combinational logic on wb_dat_o
  > lib/core_usb_*: fix up port declarations

rvpu.20260524

* gcc 2de7aa7ec48..2de7aa7ec48 (0):
  > rebased on releases/gcc-16.1.0

* binutils c8e488a26a4...90e496c406e (1):
  > rebased on binutils-2_46
  > underLineOS: enable .noinit .persistent sections

* newlib 1dafddd39...73cf55d51 (8):
  > rebased on newlib-4.6.0
  > underLineOS: macros rework
  > underLineOS: decrease SCHEDLRHZ from _MSECS(100) to _MSECS(50) ...
  > underLineOS: crt0.S: use better REG_L and REG_S assembly
  > underLineOS: _oops() if a _timer is {re,dis}-armed by a different CPU
  > underLineOS: prevent unnecessary timeslice preemption
  > underLineOS: reduce sizeof _thread_t by moving its context-switch save area to its stack
  > underLineOS: use <stddef.h> in _os.h
  > underLineOS: improve _os.h

* hw ec47d1c...04b51d8 (22):
  > rv32-orangecrab0285: rebuild bitstream and logs
  > rvxx/dcache: coherency
  > rvxx/dcache: when simulating, use faster dCache.REGMSTOUTPUT(0)
  > rvxx/dcache: remove dCacheType0; keep dCacheType1 only
  > rv32-sim: update sim.gtkw
  > rvxx: rename dcache to dCache, icache to iCache
  > rv32-sim/apps: rebuild binaries
  > rv32-sim/apps: makefile improvements
  > rv32-sim/apps/tinyraytracer: modify rendering pattern
  > rv32-sim/apps/tinyraytracer: bugfix atomic variable usage
  > rv32-sim/apps/smp_pi: use __attribute__((noinit)) where applicable
  > rv32-sim/apps/smp_pi: bugfix atomic variable usage
  > revert 6c1d952b rv32-sim/apps: use _thread_create().pin == false
  > rv32-sim/apps/tinyraytracer: do not include stack allocation in the duration
  > rv32-sim/apps/smp_pi: do not include stack allocation in the duration
  > rv32-sim/apps/coremark: print `CoreMark Size` only if errors
  > rv32-orangecrab0285: remove un-necessary use of lib/ecp5pll.sv
  > rv32-orangecrab0285: use `-dff` with `synth_ecp5`
  > rv32-orangecrab0285: improve makefile
  > dev/sram: use better RAM declaration syntax
  > lib/ram: lattice-specific attributes
  > lib/ram: remove incorrect attribute

rvpu.20260422

* newlib 885d0e998...6e59cd9ac (14):
  > underLineOS: _thread_schedoncpu(): restore preemption if needed
  > underLineOS: _thread_sched(): bugfix atomic variable usage
  > underLineOS: _thread_schedoncpu(): minimize __irq_ipi() event
  > underLineOS: improve _thread_sched()
  > underLineOS: improve _thread_kill() _thread_schedone() _thread_exit()
  > underLineOS: improve _thread_preempt()
  > underLineOS: improve _thread_sleeponwquntil()
  > underLineOS: improve _thread_stop()
  > underLineOS: make irqctrl_lock local to _os.c
  > underLineOS: fifo: improvements
  > underLineOS: mutex: improvements
  > underLineOS: _thread_sched(): do not migrate pinned thread
  > underLineOS: improve _thread_sched()
  > underLineOS: bugfix: set _thread_cur->wq before wq->l

* hw 9f592c8...ec47d1c (44):
  > rv32-orangecrab0285: rebuild bitstream and logs
  > rvxx/dcache: rename state FLUSH to WRITEB
  > rvxx/dcache: dCacheType1: rename state TESTHIT to TSTHIT
  > rvxx/dcache: dCacheType1: remove reg testhit
  > rvxx/dcache: misc changes
  > rvxx/dcache: dCacheType0: rework m_wb_bsy_o
  > rvxx/dcache: dCacheType1: rename m_wb_ack to testhit
  > rvxx/icache: default to NO_RW_CHECK
  > rvxx/pu: format return-address-stack for simulation
  > rvxx: misc README change
  > rv32-sim: implement make TRACE_LEN=
  > rv32-sim: use fst instead of vcd
  > rv32-sim: sim_vcd->sim_trace VCDTRACE_BEGIN->TRACE_BEGIN
  > rv32-sim: update sim.sav and rename to sim.gtkw
  > README
  > lib/wb_mux: workaround yosys not supporting parameter-array and array-literals
  > rename MASTER->MDEV, SLAVE->SDEV
  > lib/wb_mux: remove the use of s_wb_mapsz signal
  > dev/gpio: change mapsz from 128 to 2*sizeof(uintptr_t) bytes
  > dev/irqctrl: change mapsz from 128 to sizeof(uintptr_t) bytes
  > dev/serial: change mapsz from 128 to 2*sizeof(uintptr_t) bytes
  > dev/serial_sim: fix c9002003 implement reading from serial
  > rv32-sim/apps: rebuild binaries
  > rv32-sim/apps: use `chmod -x` on .elf and .bin files
  > rv32-sim/apps: use _thread_create().pin == false
  > rv32-orangecrab0285: improve makefile
  > rv32-sim/apps/coremark: bugfix atomic variable usage
  > rv32-sim/apps/tinyraytracer: bugfix atomic variable usage
  > lib/rstbtnctrl: Reset button controller
  > lib/skidbuf: clog2 include not needed
  > lib/dbncr: reset signal not needed
  > lib/wb_mux: precompute addrspace[] and $display() it
  > lib/wb_arbiter: bugfix: match wb_addr when unlocking
  > lib/wb_mux: bugfix a8652fea and sweep for valid slvidx only when m_wb_stb_i true
  > lib/skidbuf: implement near_bsy_o signal
  > lib/fifo: bugfix near_full_o and near_empty_o signals
  > lib/wb_mux: rename wire wb_stb to _m_wb_stb_i
  > rv32-nexysa7100: vivado optimization changes for performance
  > rv32-artya7100: vivado optimization changes for performance
  > rv32-sim/apps/coremark: increase max number of supported cores to 16
  > rv32-sim/apps/coremark: set PARALLEL_METHOD to `cores` instead of `threads`
  > rv32-sim/apps/coremark: print crc values only if errors
  > remove unnecessary logic
  > lib/wb_skidbuf: rename parameter MAXPENDINGACK to DEPTH

rvpu.20260102

* hw 53d1082...9f592c8 (72):
  > rvxx: README
  > rv32-sim: update sim.sav
  > rv32-orangecrab0285: binaries and logs updates
  > lib/xc7pll_100_to_50_100_200
  > use XWORDBITSZ as makefile defined in top level file
  > rv32-sim/apps: fixup makefiles to generate {32,64,128,256}.hex
  > rvxx/dcache: fully specify if() block
  > rv32-orangecrab0285: set sram.INITFILE from makefile
  > rv32-orangecrab0285: fixup pll instantiation
  > rv32-orangecrab0285: yosys: report passing Max Freq
  > lib/ecp5pll: lib/ecp5pll: misc improvements
  > rv32-orangecrab0285: better log names
  > rvxx/dcache: misc changes
  > rvxx/dcache: fix dCache_m_dat_r use before its declaration
  > rvxx/pu: misc re-arrangements
  > rvxx/pu: rename `Branch History Table` to `Branch Prediction Table`
  > rvxx/dcache: decrease cache evictions when more than 1 way
  > wishbone: replace signal `tag` by signal `lock`
  > rvxx: turn input id_i into parameter PUID
  > rvxx/dcache: remove __dCache_m_stb_i
  > rvxx/dcache: type0: include conly_r check in cache_hit logic
  > rvxx/dcache: type1: remove cmiss_r check from cache_hit logic
  > rvxx/dcache: type0: improve cache_drt_i
  > rvxx/dcache: Comment-out unnecessary logic
  > rvxx/dcache: atomic operations always cache-miss
  > rvxx/dcache: misc changes for clarity
  > rvxx/dcache: always use dcache.TYPE(1)
  > rvxx/dcache: Comment-out unnecessary logic
  > rvxx/dcache: cmiss_r should also be checked when (!cache_miss)
  > rv32-sim: use dcache type1 by default
  > rv32-orangecrab0285: use dcache type1 by default
  > rvxx/dcache: bugfixes and improvements
  > rvxx/cpu: implement USEMEMCLKDOMAIN (use memory clock domain)
  > rvxx: prevent insn fetch interruption (while maintaining data priority)
  > lib/wb_mux: restart slvidx computation if m_wb_addr_i changes mid-computation
  > lib/wb_arbiter: decouple requests from responses
  > wishbone: remove signal `cyc` and add signal `tag`
  > rvxx/memctrl: misc improvements
  > rvxx/dcache: rework logic setting dCache_m_*_i signals
  > rvxx/lsu: convert ldUnit_rqsts from fifo to fifo_fwft
  > rvxx/dcache: optimize how dCache_m_pending_acks gets used
  > rvxx/dcache: simplify __dCache_m_stb_i
  > rvxx/dcache: rename EVICT to FLUSH
  > rvxx/dcache: misc optimizations
  > rvxx: compute AMO without Lr and Sc at iF stage
  > lib/uart: misc change
  > lib/serial: misc change
  > lib/uart/uart_fifo_phy: bugfix tx_read_stb
  > lib/wb_skidbuf: fix how s_wb_pending_acks is used
  > lib/wb_cdc: fix how m_wb_pending_acks is used
  > lib/wb_mux: fix how ack_pending is used
  > rvxx/dcache: consolidate dCache implementations
  > rvxx/dcache: fix how ack_pending is used
  > rvxx/dcache: remove REGMASTROUT
  > rvxx/dcache: remove REGCACHEHIT
  > rvxx/dcache: misc re-arrangements
  > rv32-orangecrab0285: make ICACHESZ and DCACHESZ 16
  > rv32-nexysa7100: make ICACHESZ and DCACHESZ 16
  > rv32-artya7100: make ICACHESZ and DCACHESZ 16
  > rvxx/pu: misc rearrangements
  > rvxx/pu: improve register forwarding
  > rvxx/pu: simplify how iD_rW_rdId_isTrue get set
  > rvxx/pu: misc name fixes of signals used to set iD_stalled
  > rvxx/pu: smaller Return-Address-Stack registers
  > rvxx/pu: alu: use a single shiftter for left and right shifts
  > rvxx/pu: document eX_stalled
  > lib/clog2: use systemVerilog compound assignment operators
  > rvxx: rename lateWriteback and "late writeback" to lateResult.
  > rvxx/dcache: misc fixes to dCache signal names
  > rvxx/lsu: improve ldUnit_rqsts_full documentation
  > rvxx/cpu: misc fixes to branch prediction signal names
  > rvxx/cpu: remove iF_insn_ and use iCache_dato_w directly

rvpu.20250930

* newlib 6812e2073...3ad008d92 (4):
  > underLineOS: _thread_sched() to use cpu with least number of threads
  > underLineOS: rename __timer_preempt() to __timeslice_preempt()
  > underLineOS: restore the _thread_t field `timeleft`
  > underLineOS: restore the field scheddate of struct __runq

* hw 09ebdc7...39b91f1 (5):
  > rv32-sim/apps: rebuilt
  > rv32-sim/apps/thrdtst: misc improvements
  > rv32-sim/apps/tinyraytracer: misc improvements
  > rv32-sim/apps/smp_pi: misc improvements
  > rv32-sim/apps/coremark: misc fixes

rvpu.20250918

* newlib 3bddb669f...ece7a2207 (7):
  > underLineOS: remove the field cycle of _trap_savedctx_t
  > underLineOS: apply RISC-V required stack alignment
  > underLineOS: do not use malloc_usable_size()
  > underLineOS: remove _schedlr_freq()
  > underLineOS: rename `scheduled preemption` to `timeslice preemption`
  > underLineOS: move __irq_disabled to _thread_t
  > underLineOS: remove the field scheddate of struct __runq

* hw ec1a96b...09ebdc7 (2):
  > rv32-sim/apps: rebuilt
  > rv32-sim/apps/thrdtst: remove the use of _trap_savedctx()->cycle

rvpu.20250910

* gcc 831c75a09c9...cd715489529 (1):
  > make -msmall-data-limit= default value 0

* newlib 2b6fa6c2a...ae194cdc8 (9):
  > ran autoreconf2.69 in libgloss/
  > underLineOS: partially revert 6bb974bce optimize __runq[] usage
  > underLineOS: better document SCHEDLRHZ
  > underLineOS: use noinline on __printdec() __printstr()
  > underLineOS: make newlib syscalls weak symbols
  > underLineOS: remove the _thread_t field `ts`
  > underLineOS: remove generating libsim.a
  > underLineOS: improve stdin
  > underLineOS: improve _thread_sleeponwquntil()

* riscv-gnu-toolchain 2d540ae...9ab379a (1):
  > adjust newlib build flags

* hw 32ef649...ec1a96b (3):
  > rv32-sim/apps: rebuilt
  > rv32-sim/apps: add `-Wl,-z,max-page-size=4` to CFLAGS
  > thrdtst: rename __printstr() to printstr()

rvpu.20250827

* binutils 31a658e0e76...73f14b2b4e8 (1):
  > underLineOS: move _thread_cur to start of TLS data

* newlib 77fa17ee9...cdfc99eed (15):
  > underLineOS: bugfix ___switchctx()
  > underLineOS: bugfix thread termination
  > underLineOS: bugfix handling of timer interrupt
  > underLineOS: fix __trap() while handling another trap
  > underLineOS: optimize __runq[] usage
  > underLineOS: __switchctx() definition cosmetic change
  > underLineOS: remove _tpval() and use _thread_cur instead
  > underLineOS: remove un-necessary use of _atomic functions
  > underLineOS: Registers tp and gp do not need to be saved
  > underLineOS: move _thread_cur to start of TLS data
  > underLineOS: fix _fifo_put() _fifo_get() to keep sleeping until timeout
  > underLineOS: improve _fifo_get() when flushing
  > underLineOS: remove un-necessary use of volatile
  > underLineOS: improve how _mutex_t.acqcnt is used
  > underLineOS: better _preempt_disable() use

* hw 0e12954...32ef649 (2):
  > updated apps binaries
  > dev: improve documentation