AXI4 with a FIFO integrated with VIP

A pleasant note-taking platform.

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

RiscSoC 是一个芯片集成项目，包含了 Cortex-M0、Cortex-M3、MIPS、RISC-V、4-BIT 等内核的 SoC 集成，部分 SoC 使用的自己设计的内核

Verification of pulpino subsystem consisting of AXI input interface and SPI as output interface

FPGA-based USB fast communication using FT232H/FT600 chip.

FPGA-based RISC-V CPU+SoC.

FPGA-based 14bit DAC with resistance network and PWM.

Test suite designed to check compliance with the SystemVerilog standard.

EE-599f SoC SystemVerilog Final Project

In this repository, the RTL design and verification of the axi2apb bridge communication protocol are realized. In this system, the preferred AXI bus will be axi4-lite and the APB bus will be APB3. …

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improv…

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

Functional Coverage and Constrained Randomization Extensions for Cocotb

Examples with UVM

Contains the code examples from The UVM Primer Book sorted by chapters.

AMBA bus generator including AXI, AHB, and APB

Various HDL (Verilog) IP Cores

FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge

一个很好用的串口示波器。

UVM 1.2 port to Python

80186 compatible SystemVerilog CPU core and FPGA reference design