ARM AMBA 4 AXI4,AXI4-lite,AXI4-stream SVAs (BP063) MiscellaneousBP063

A professional cross-platform SSH/Sftp/Shell/Telnet/Tmux/Serial terminal.

Verilog formatter

FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software

AMBA bus generator including AXI, AHB, and APB

Contains commonly used UVM components (agents, environments and tests).

The root repo for lowRISC project and FPGA demos.

IC design and development should be faster，simpler and more reliable

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

A wishbone controlled scope for FPGA's

建议大家star此仓库，仓库会持续更新。由于部分淘宝卖家“借鉴”实验室出品的nanoDAP详情描述和资料，请大家认准实验室官方链接

80186 compatible SystemVerilog CPU core and FPGA reference design

一个很好用的串口示波器。

USB3 PIPE interface for Xilinx 7-Series

Small footprint and configurable PCIe core

A full-speed device-side USB peripheral core written in Verilog.

HDL libraries and projects

Open source FPGA-based NIC and platform for in-network compute

This repository provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the mixed-mode clock manager (MMCM) for the Xilinx® 7 series FPGA

DEPRECATED mbed HDK - This repository is not being maintained. For the latest updates, please use: https://github.com/ARMmbed/mbed-HDK-Eagle-Projects

Source code of MIPI DSI Bridge Published on https://www.circuitvalley.com

SystemVerilog realization of RISC-V processor

Generate UVM testbench framework template files with Python 3

An FPGA-based FT232H/FT600 chip controller for rapid data transmission via USB. 使用FT232H/FT600芯片进行FPGA与电脑之间的高速数据传输。

learning notes of SystemVerilog与功能验证

uvm AXI BFM(bus functional model)

an easy bus verification example based on UVM/SV framework

This is a course design of GDUT, with the instruction of GuangPing Li associate professor

⏬ Dumb downloader that scrapes the web