cocotb: Python-based chip (RTL) verification

HDL libraries and projects

Git Extensions is a standalone UI tool for managing git repositories. It also integrates with Windows Explorer and Microsoft Visual Studio (2015/2017/2019).

⏬ Dumb downloader that scrapes the web

FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software

A Python package with bindings to the "Virtual Instrument Software Architecture" VISA library, in order to control measurement devices and test equipment via GPIB, RS232, or USB.

Small footprint and configurable PCIe core

USB3 PIPE interface for Xilinx 7-Series

Verilog formatter

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

Libraries for STM32 (STM32F103C8T6) on pure CMSIS.

A professional cross-platform SSH/Sftp/Shell/Telnet/Tmux/Serial terminal.

Open source FPGA-based NIC and platform for in-network compute

An FPGA-based FT232H/FT600 chip controller for rapid data transmission via USB. 使用FT232H/FT600芯片进行FPGA与电脑之间的高速数据传输。

建议大家star此仓库，仓库会持续更新。由于部分淘宝卖家“借鉴”实验室出品的nanoDAP详情描述和资料，请大家认准实验室官方链接

Source code of MIPI DSI Bridge Published on https://www.circuitvalley.com

80186 compatible SystemVerilog CPU core and FPGA reference design

A wishbone controlled scope for FPGA's

This is a course design of GDUT, with the instruction of GuangPing Li associate professor

The root repo for lowRISC project and FPGA demos.

ARM AMBA 4 AXI4,AXI4-lite,AXI4-stream SVAs (BP063) MiscellaneousBP063

A full-speed device-side USB peripheral core written in Verilog.

IC design and development should be faster，simpler and more reliable

AMBA bus generator including AXI, AHB, and APB

一个很好用的串口示波器。

This repository provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the mixed-mode clock manager (MMCM) for the Xilinx® 7 series FPGA

learning notes of SystemVerilog与功能验证

AMBA AHB 2.0 VIP in SystemVerilog UVM

Generate UVM testbench framework template files with Python 3