⏬ Dumb downloader that scrapes the web

A professional cross-platform SSH/Sftp/Shell/Telnet/Tmux/Serial terminal.

Git Extensions is a standalone UI tool for managing git repositories. It also integrates with Windows Explorer and Microsoft Visual Studio (2015/2017/2019).

cocotb: Python-based chip (RTL) verification

Open source FPGA-based NIC and platform for in-network compute

IC design and development should be faster，simpler and more reliable

HDL libraries and projects

FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software

建议大家star此仓库，仓库会持续更新。由于部分淘宝卖家“借鉴”实验室出品的nanoDAP详情描述和资料，请大家认准实验室官方链接

A Python package with bindings to the "Virtual Instrument Software Architecture" VISA library, in order to control measurement devices and test equipment via GPIB, RS232, or USB.

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

Small footprint and configurable PCIe core

一个很好用的串口示波器。

The root repo for lowRISC project and FPGA demos.

80186 compatible SystemVerilog CPU core and FPGA reference design

An FPGA-based FT232H/FT600 chip controller for rapid data transmission via USB. 使用FT232H/FT600芯片进行FPGA与电脑之间的高速数据传输。

uvm AXI BFM(bus functional model)

USB3 PIPE interface for Xilinx 7-Series

A full-speed device-side USB peripheral core written in Verilog.

Verilog formatter

DEPRECATED mbed HDK - This repository is not being maintained. For the latest updates, please use: https://github.com/ARMmbed/mbed-HDK-Eagle-Projects

AMBA AHB 2.0 VIP in SystemVerilog UVM

AMBA bus generator including AXI, AHB, and APB

Source code of MIPI DSI Bridge Published on https://www.circuitvalley.com

A wishbone controlled scope for FPGA's

Libraries for STM32 (STM32F103C8T6) on pure CMSIS.

Contains commonly used UVM components (agents, environments and tests).

Generate UVM testbench framework template files with Python 3

This is a course design of GDUT, with the instruction of GuangPing Li associate professor

This repository provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the mixed-mode clock manager (MMCM) for the Xilinx® 7 series FPGA