Verilog Ethernet components for FPGA implementation

free5GRAN is an open-source 5G RAN stack. The current version includes a receiver which decodes MIB & SIB1 data. It also acts as a cell scanner. free5GRAN works in SA mode.

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

AXI4 and AXI4-Lite interface definitions and testbench utilities

Common SV components

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

HDL libraries and projects

Verilog AXI components for FPGA implementation

This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.

Generator of verilog description for FPGA MobileNet implementation

The Altera Avalon bus IP core for TI AIC1106 PCM Codec and Software Driver Example

Open Source HLx Examples

在FPGA上面实现一个NPU计算单元。能够执行矩阵运算（ADD/ADDi/ADDs/MULT/MULTi/DOT等）、图像处理运算（CONV/POOL等）、非线性映射（RELU/TANH/SIGM等）。

CNN acceleration on virtex-7 FPGA with verilog HDL

16-APSK DVB-S2 Transmitter for BladeRF

Six snippets of code that made deep learning what it is today.

Unconstrained function minimization in Javascript

Embedded Team documents, how-to, trainings, etc...

Automatically exported from code.google.com/p/tlk2501-fpga

Chinese chess, a strategy board game for two players.

Sudoku solvers in Python, Clojure, Haskell, Ruby, etc. Based on Peter Norvig's constraint propagation and search algorithm.