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数字IC相关资料

DPLL for phase-locking to 1PPS signal

Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.

An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.

提取图像的灰度共生矩阵（GLCM），根据GLCM求解图像的概率特征，利用特征训练SVM分类器，对目标分类

An efficient implementation of the Viterbi decoding algorithm in Verilog

free5GRAN is an open-source 5G RAN stack. The current version includes a receiver which decodes MIB & SIB1 data. It also acts as a cell scanner. free5GRAN works in SA mode.

DVB-S2 and DVB-T2 receiver blocks for GNU Radio

16-APSK DVB-S2 Transmitter for BladeRF

Verilog Ethernet components for FPGA implementation

Verilog AXI components for FPGA implementation

SmartFusion2 Security Evaluation Kit sample RISC-V Libero project(s)

Documenting the Xilinx 7-series bit-stream format.

Reverse-engineering tools for FPGA bitstreams, Altera and Xilinx

Bitfile Interpretation Library for Xilinx Virtex FPGAs

HDL libraries and projects

An Open Source configuration of the Arty platform

CDMA communication system using Matlab. #github

An OpenCL-based FPGA Accelerator for Convolutional Neural Networks

An open-source microcontroller system based on RISC-V

Python Productivity for ZYNQ