Zeek is a powerful network analysis framework that is much different from the typical IDS you may know.

a verilog project trying to implement an ethernet mac controller composed with different modules

PCIE core

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Infiniband Verbs Performance Tests

Verilog PCI express components

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

32-bit Superscalar RISC-V CPU

手把手撕LeetCode题目，扒各种算法套路的裤子。English version supported! Crack LeetCode, not only how, but also why.

[mirror] Go supplementary cryptography libraries

Project Wycheproof tests crypto libraries against known attacks.

SI6 Networks' IPv6 Toolkit

RIOT - The friendly OS for IoT

Design ARM LEGv8 Architecture

64-bit ARM processor for Computer Architecture course at Rowan University

note: this is a github copy of a hardware project hosted on bitbucket.

Tools for testing kernel ciphers and hash algorithm

C/C++ & Unix

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

An Arm V8 processor with pipelining made via the instructions of the ARM-Edition book written by David A. Patterson & John L. Hennesey

A experiment for Computer Organization and System Structure, using Verilog

ETeam软件工程协作工具

32-bit RISC-V system on chip for iCE40 FPGAs

Argo is a time-division multiplexing network-on-chip.

IceChips is a library of all common discrete logic devices in Verilog

Simulation only cartridge NeoGeo hardware definition

Dual IPv4/IPv6 Stack