Skip to content
View gongfna's full-sized avatar

Block or report gongfna

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results

Verilog-based PCIe Endpoint core design implementing Physical, Data Link, and Transaction layers. Includes link training, DLLP/TLP handling, BAR configuration, and AXI interface. Focused on modular…

Verilog 2 Updated Feb 18, 2026

Verilog PCI express components

Verilog 1,559 398 Updated Apr 26, 2024

In this repository you will find the open source code for the MKA daemon implemented by Technica Engineering Gmbh. The GPL version supports running in Linux, and implements MKA as defined in IEEE80…

C 20 6 Updated Nov 20, 2025

Linux kernel source tree

C 225,423 61,281 Updated Mar 28, 2026

32-bit Superscalar RISC-V CPU

Verilog 1,208 202 Updated Sep 18, 2021

RISC-V CPU Core (RV32IM)

Verilog 1,683 279 Updated Sep 18, 2021

CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations

Verilog 21 6 Updated May 4, 2017

Install Boot2Docker cli, msys-git and VirtualBox

Inno Setup 1,207 357 Updated Aug 12, 2015