Skip to content
View hyrious's full-sized avatar
💤
lazy
💤
lazy
258 followers · 60 following

Achievements

Achievement: Galaxy BrainAchievement: YOLOAchievement: QuickdrawAchievement: Pull Sharkx3Achievement: StarstruckAchievement: Arctic Code Vault Contributor

Achievements

Achievement: Galaxy BrainAchievement: YOLOAchievement: QuickdrawAchievement: Pull Sharkx3Achievement: StarstruckAchievement: Arctic Code Vault Contributor

Highlights

  • Pro

Organizations

@wopjs

Block or report hyrious

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Stars

2 stars written in Verilog
Clear filter

darklife / darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Verilog 2,455 319 Updated Jul 16, 2025

ultraembedded / riscv

RISC-V CPU Core (RV32IM)

Verilog 1,600 275 Updated Sep 18, 2021