Tags: icewm/RADAR

AERIS-10 2048-pt FFT Upgrade + Full Timing Closure

2048-pt FFT with decimation=4: 512 output bins at 6m spacing (was 64 bins
at 24m). Complete cross-layer upgrade spanning FPGA RTL, Python GUI,
MCU firmware, golden references, and CI test suite. All 5 FPGA clock
domains timing-closed on xc7a50tftg256-2.

FFT/DSP upgrade:
- 2048-pt FFT engine (was 1024), 4x decimation (was 16x)
- 512 range bins at 6m spacing, max range 3,072m (was 64 bins, 24m, 1,536m)
- 9-bit range bin addressing (was 6-bit), 14-bit Doppler addressing (was 11-bit)
- 2-segment chirp loader (was 4), 6-bit stream control (was 3-bit)
- Bulk USB per-frame format with Manhattan magnitude (FT2232H rewrite)

FPGA timing closure (Builds 17-19):
- Build 17: WNS=-0.331ns (57 failing endpoints in cfar_ca.v mux trees)
- Build 18: CFAR pipeline fix closes clk_100m (WNS=+0.013ns)
- Build 19: CIC reset path fix closes clk_mmcm_out0 (WNS=+0.068ns)
- All 5 clock domains met, 0 failing endpoints

BRAM inference fixes:
- mti_canceller.v prev_i/q arrays: async reset -> sync reset for BRAM
- matched_filter overlap_cache: sync-only write block for BRAM inference

Cross-layer updates:
- Python GUI (radar_protocol.py, GUI_V65_Tk.py, V7 PyQt6): 512-bin arrays,
  6m range scale, 6-bit stream control, bulk frame parser
- MCU firmware: max_distance 1536->3072, map_size 1536->3072
- All golden data regenerated for 2048/512 config
- CI: 285 tests (172 Python + 22 MCU + 30 FPGA + 61 cross-layer), 0 failures

AERIS-10 Hybrid AGC System + FPGA Timing Hardening

Full hybrid AGC implementation spanning FPGA, STM32, and GUI layers
with FPGA timing margin improvements and two rounds of code review fixes.

AGC system:
- FPGA inner loop: per-sample rx_gain_control with saturation tracking
- STM32 outer loop: per-frame ADAR1000 VGA common gain adjustment
- GUI: AGC controls, status readback, real-time visualization widget
- Registers 0x28-0x2C: enable, target, attack, decay, holdoff

FPGA timing hardening (400MHz WNS: +0.002ns → +0.339ns):
- DONT_TOUCH on BUFG to prevent AggressiveExplore cascade replication
- NCO→mixer pipeline registers break critical 1.5ns route
- Clock uncertainty reduced 200ps→100ps

Code review fixes (20 bugs across two rounds):
- STM32: uint32_t underflow guard, snprintf buffer safety, error masking
- GUI: opcode set conflict, V7 diagnostics wiring, replay mode label
- FPGA: comment corrections, golden reference updates
- CI: test_v7.py added to pytest command

Vivado Build 27: WNS=+0.080ns, WHS=+0.056ns, zero violations
Tests: 120 Python + 21 MCU + 25 FPGA + 29 cross-layer = 195 total
Device: xc7a50tftg256-2 (speed grade -2)

feat: hybrid AGC (FPGA phases 1-3 + GUI phase 6) with timing fix

FPGA:
- rx_gain_control.v rewritten: per-frame peak/saturation tracking,
  auto-shift AGC with attack/decay/holdoff, signed gain -7 to +7
- New registers 0x28-0x2C (agc_enable/target/attack/decay/holdoff)
- status_words[4] carries AGC metrics (gain, peak, sat_count, enable)
- DIG_5 GPIO outputs saturation flag for STM32 outer loop
- Both USB interfaces (FT601 + FT2232H) updated with AGC status ports

Timing fix (WNS +0.001ns -> +0.045ns, 45x improvement):
- CIC max_fanout 4->16 on valid pipeline registers
- +200ps setup uncertainty on 400MHz domain
- ExtraNetDelay_high placement + AggressiveExplore routing

GUI:
- AGC opcodes + status parsing in radar_protocol.py
- AGC control groups in both tkinter and V7 PyQt dashboards
- 11 new AGC tests (103/103 GUI tests pass)

Cross-layer:
- AGC opcodes/defaults/status assertions added (29/29 pass)
- contract_parser.py: fixed comment stripping in concat parser

All tests green: 25 FPGA + 103 GUI + 29 cross-layer = 157 pass

AERIS-10 50T Production Build — FT2232H USB 2.0 Interface

Vivado Build 15 bitstream for XC7A50T-FTG256 with FT2232HQ USB 2.0 (8-bit)
interface replacing FT601 USB 3.0 (32-bit) for the production board.

Key changes:
- Parametric USB_MODE in radar_system_top.v (MODE=0: FT601, MODE=1: FT2232H)
- radar_system_top_50t wrapper with USB_MODE=1
- usb_data_interface_ft2232h.v: 8-bit 245 Synchronous FIFO
- DDC retiming fix for 400MHz timing closure
- Python host cleanup: FT601 removed, FT2232HConnection only
- Full CI: 101 tests (58 Python + 20 MCU + 23 FPGA)

Timing: WNS=+0.088ns, zero violations
Device: xc7a50tftg256-2 (speed grade -2)
LUTs: 10060/32600 (30.9%), FFs: 12670/65200 (19.4%)
BRAM: 17.5/75 (23.3%), DSP48: 112/120 (93.3%)