Collaborative cheatsheets for console commands 📚.

RISC-V Instruction Set Manual

tsParticles - Easily create highly customizable JavaScript particles effects, confetti explosions and fireworks animations and use them as animated backgrounds for your website. Ready to use compon…

OpenTitan: Open source silicon root of trust

FreeBSD adapted for CHERI-RISC-V and Arm Morello.

Yosys Open SYnthesis Suite

Chisel: A Modern Hardware Design Language

The most popular HTML, CSS, and JavaScript framework for developing responsive, mobile first projects on the web.

Verilator open-source SystemVerilog simulator and lint system

XLS: Accelerated HW Synthesis

cocotb: Python-based chip (RTL) verification

Verilog to Routing -- Open Source CAD Flow for FPGA Research

Multi-platform nightly builds of open source digital design and verification tools

Modular hardware build system

An Open-source FPGA IP Generator

A beautiful, simple, clean, and responsive Jekyll theme for academics

Machine learning on FPGAs using HLS

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

The simulator for the Next-Generation Championship in Branch Prediction (CBP-NG)

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Random instruction generator for RISC-V processor verification

RISC-V Packed SIMD Extension

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

This repository contain source code for new flow of FreeEDA now know as eSim

eXtensible Heterogeneous Energy-Efficient Platform based on RISC-V

ESP8266 core for Arduino

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy