Onboarding project for new members

Dromajo ESESC

Memory Marionette Model

Memory Marionette Model

QEMU libsystemctlm-soc co-simulation demos.

DPI module for UART-based console interaction with Verilator simulations

A Pi emulating a GameBoy sounds cheap. What about an FPGA?

LEVEL: Open-source RV32IMC RISC-V processor core with pipelined microarchitecture, cache support, SoC peripherals and verification framework.

Baremetal console firmware for RISC-V with AIA (Advanced Interrupt Architecture)

🌊 Digital timing diagram rendering engine

A roadmap for those who want to build a career as an FPGA / ASIC Engineer

Veryl: A Modern Hardware Description Language

An experimental minimal musl based distro

Hardcaml is an OCaml library for designing hardware.

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)

A List of Free and Open Source Hardware Verification Tools and Frameworks

Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra

Referance XDMA HBM design for U55C

A self-contained online book containing a library of FPGA design modules and related coding/design guides.

Parameterized hardware generators for cryptographic primitives (modular arithmetic, NTT, polynomial ops) targeting FHE, ZKP, and PQC accelerators

Risc-v cpu testing component (Testbench) written in sv and c++

An ECP5 FPGA Dev Board in a Pi Zero form

An RF frontend IC for the LinHT project, used as an I and Q modulator/demodulator

Digital Design Equivalence Checking

Modern C++HDL architecture of 400G-800G SmartNIC based on own optimized RISC-V

HAL – The Hardware Analyzer

Universal utility for programming FPGA

A verification tool for many memory models

SystemVerilog design elaborator into word-level netlist form

Turn any codebase, with its docs, SQL schemas, configs, and PDFs, into a queryable knowledge graph. A /graphify skill for Claude Code, Cursor, Codex, and Gemini CLI: local deterministic AST parsing…