Skip to content
View jeanminet's full-sized avatar

Organizations

@Koheron

Block or report jeanminet

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results
C++ 11 1 Updated Oct 6, 2025

A small second stage boot loader to start Linux on Zynq-7000

C 1 2 Updated Feb 24, 2025

FPGA Clock Configuration Device Driver for Linux

C 33 7 Updated Dec 4, 2025

Implementation of koheron-server which can be ported to third-part designs

C++ 2 Updated Jun 21, 2022

SDK for FPGA / Linux Instruments

C 1 Updated Jun 29, 2026

Koheron based 4x ADC upsampling

Tcl 1 Updated Sep 22, 2018

Digital Phase-locked-loop software for Locking a Frequency Comb using a Red Pitaya

Python 51 40 Updated Jun 29, 2026

Minimal printf() implementation for embedded projects.

C 183 58 Updated Oct 28, 2023

The official Xilinx u-boot repository

C 682 850 Updated Aug 15, 2026

Advanced DAQ Tools for the RedPitaya (STEMlab 125-14)

C 45 13 Updated Jun 24, 2026

This is a guide for bringing up custom ZYNQ boards. It covers test sequence, test method, common error situations and code and project that can help to investigate a bring-up problem.

Tcl 72 15 Updated Oct 5, 2017

pyrpl turns your RedPitaya into a powerful DSP device, especially suitable as a lockbox in quantum optics experiments.

HTML 204 141 Updated Aug 9, 2026

Library for the numerical simulation of closed as well as open quantum systems.

Julia 619 144 Updated Aug 14, 2026

Open PicoBlaze Assembler

Python 65 13 Updated Oct 29, 2023

Simple C snippet to transfer DMA memory with scatter/gather on a Zynq 7020

C 59 28 Updated Apr 27, 2017

FPGA SoC devices build infrastructure for GNU Linux based on Autotools

Tcl 6 3 Updated Jan 28, 2021

Linux device tree generator for the Xilinx SDK (Vivado > 2014.1)

Tcl 239 206 Updated Jun 15, 2026

Python Productivity for ZYNQ

Jupyter Notebook 2,334 860 Updated Aug 14, 2026

The C++ Core Guidelines are a set of tried-and-true guidelines, rules, and best practices about coding in C++

CSS 45,247 5,552 Updated Aug 6, 2026

Attractive JavaScript charts for jQuery

JavaScript 5,909 1,537 Updated Nov 8, 2023

Generates Makefiles to synthesize, place, and route verilog using Vivado

Tcl 101 23 Updated May 24, 2022

The systemd System and Service Manager

C 16,598 4,623 Updated Aug 15, 2026

HackAday Cortex Kit

KiCad Layout 17 3 Updated Aug 13, 2016

Fork of linux-stable.git with my patches for zynq-based boards (Zed, Z-Turn MYIR..)

C 16 14 Updated Jul 4, 2019

Yosys Open SYnthesis Suite

C++ 4,672 1,140 Updated Aug 14, 2026

Verilog AXI stream components for FPGA implementation

Python 912 277 Updated Feb 27, 2025

A VCD parser object

Python 41 15 Updated Jul 17, 2013

BR2_EXTERNAL bsp for redpitaya

Tcl 8 4 Updated Jan 31, 2026

PeripheralOnDemand, SoC tool to simplify IP assembly around Wishbone (mainly)

Python 5 2 Updated Jun 9, 2026
Next