Skip to content
View jimjiang2's full-sized avatar

Block or report jimjiang2

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results

Raspberry pico / RP2040 based USB to I3C converter with Python support

C 92 13 Updated Jun 25, 2026

LLM inference server with continuous batching & SSD caching for Apple Silicon — managed from the macOS menu bar

Python 18,158 1,549 Updated Jul 24, 2026

🤖 Optimize LLM inference on Mac with continuous batching and SSD caching managed from your menu bar for efficient performance.

Python 8 Updated Jul 25, 2026
HTML 83 21 Updated Jan 6, 2026

用于FPGA板卡的自动硬件逆向工具,无需拆焊芯片即可获取io信息。

C 7 2 Updated May 18, 2024
Python 3 1 Updated Sep 3, 2025
C++ 76 10 Updated Jul 16, 2026

Pick your favorite language to verify your chip.

C++ 93 17 Updated Jul 15, 2026

Verilog Ethernet components for FPGA implementation

Verilog 1 Updated Jul 18, 2024

SPI-Flash XIP Interface (Verilog)

Verilog 52 13 Updated Oct 24, 2021

This project is the location of the FPGA io output with the UART serial port. Used to confirm the GPIO binding relationship of the FPGA. It is especially suitable for some FPGA boards that need to …

Verilog 2 1 Updated May 17, 2024

通用IO测试工程,用于捡垃圾测试IO。与BSDL需要对引脚输入不同,该工程只需要确定时钟输入,然后自动向每个IO发送指定字符串,因此只需要将串口接入任意IO查看输出即可

19 1 Updated Jul 17, 2025

A Flexible Framework for Experiencing Heterogeneous LLM Inference/Fine-tune Optimizations

Python 19,013 1,483 Updated Jul 24, 2026
SystemVerilog 59 11 Updated Mar 10, 2025

Python-based Hardware Design Processing Toolkit for Verilog HDL

Python 798 212 Updated Jun 15, 2024

Get up and running with Kimi-K2.6, GLM-5.2, MiniMax, DeepSeek, gpt-oss, Qwen, Gemma and other models.

Go 176,833 17,105 Updated Jul 25, 2026

Ch341dll wrap for Octave to access I2C SPI and GPIO on Windows. And a demo to drive a I2C elod(0.9 inch).

C 2 Updated Dec 19, 2021

CircuitPython module for the SI5351 clock generator.

Python 1 Updated Aug 12, 2024
Python 14 4 Updated Jun 12, 2022

SPDReader 是一个读取内存SPD信息的工具,支援DDR4&DDR5, AMD与Intel 平台均适用.

10 4 Updated Oct 14, 2023

Skeletal repository for GNU Radio WBFM implementation on Pynq board

Tcl 13 1 Updated Jun 15, 2017

Make Baidu EdgeBoard Lite as a general Zynq FPGA development board

Python 35 15 Updated Aug 7, 2023

Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)

VHDL 205 37 Updated Sep 9, 2023

Microsoft Catapult FPGA, Catapult V3, PCIE Test Demo, On-board usb Blaster and OpenCL BSP

Verilog 68 14 Updated Nov 12, 2022
Python 76 32 Updated Jul 30, 2021

数字IC相关资料

1 Updated Nov 17, 2020

Framework for hardware test fixtures and automatic test environments

Python 30 22 Updated Jul 24, 2026

Python packages providing a library for Verification Stimulus and Coverage

Python 147 32 Updated Jul 5, 2026
Next