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Raspberry pico / RP2040 based USB to I3C converter with Python support
LLM inference server with continuous batching & SSD caching for Apple Silicon — managed from the macOS menu bar
🤖 Optimize LLM inference on Mac with continuous batching and SSD caching managed from your menu bar for efficient performance.
Verilog Ethernet components for FPGA implementation
This project is the location of the FPGA io output with the UART serial port. Used to confirm the GPIO binding relationship of the FPGA. It is especially suitable for some FPGA boards that need to …
通用IO测试工程,用于捡垃圾测试IO。与BSDL需要对引脚输入不同,该工程只需要确定时钟输入,然后自动向每个IO发送指定字符串,因此只需要将串口接入任意IO查看输出即可
A Flexible Framework for Experiencing Heterogeneous LLM Inference/Fine-tune Optimizations
Python-based Hardware Design Processing Toolkit for Verilog HDL
Get up and running with Kimi-K2.6, GLM-5.2, MiniMax, DeepSeek, gpt-oss, Qwen, Gemma and other models.
Ch341dll wrap for Octave to access I2C SPI and GPIO on Windows. And a demo to drive a I2C elod(0.9 inch).
CircuitPython module for the SI5351 clock generator.
SPDReader 是一个读取内存SPD信息的工具,支援DDR4&DDR5, AMD与Intel 平台均适用.
Skeletal repository for GNU Radio WBFM implementation on Pynq board
Make Baidu EdgeBoard Lite as a general Zynq FPGA development board
Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)
Microsoft Catapult FPGA, Catapult V3, PCIE Test Demo, On-board usb Blaster and OpenCL BSP
Framework for hardware test fixtures and automatic test environments
Python packages providing a library for Verification Stimulus and Coverage