The project is aiming to manufacture custom-made PCB of Embedded MPUs(most having ARM cores; specially-designed for specified usage, slim in dimension).
Author: jlywxy(jlywxy@outlook.com)
License: GPLv2
Important:
Check board/readme.PCB_DESIGN_STATUS.md before actual PCB manufacture process.
Use verified boards only.
Status of Working Boards:
| Code | Chipset | Core DRAM Clock |
PCB Stack EDA |
Status |
|---|---|---|---|---|
| Hypericum | Allwinner A20 | 1.2GHz 2x Cortex-A7 400MHz(800Mbps) DDR3 |
4-layer KiCad |
✅final-pcb |
| Carambola | Atmel AT91SAM9G25 | 400MHz ARM926EJ-S 133MHz(266Mbps) DDR2 |
4-layer KiCad |
✅final-pcb |
| Apricot B | Samsung S3C2416X | 400MHz ARM926EJ-S 133MHz(266Mbps) DDR2 |
4-layer LCEDA |
pcb-revision |
| Almond B | Samsung S3C2410 | 200MHz ARM920T 133MHz SDR |
4-layer KiCAD |
pcb-revision |
| Azalea | Rockchip RK3128 | 1.1GHz 4x Cortex-A7 533MHz(1066Mbps)DDR3 |
4-layer Cadence |
pre-sch |
| Clematis | Rockchip RK3188 | 1.1GHz 4x Cortex-A9 533MHz(1066Mbps)DDR3 |
4-layer KiCad |
pre-sch |
| Cumquat (*SlimMIPS) |
MediaTek MT7620A | 580MHz MIPS24KEc 192MHz(384Mbps) DDR2 |
4-layer KiCAD & Cadence(two versions) |
pre-sch |
Project Pipeline: planning -> avail-analyse -> pre-sch -> pcb-fab-test(1-stage pcb) -> software-test -> post-sch -> pcb-revision -> post-pcb-fab-test -> final-pcb -> post-software-test -> done
(this column started tracking from 2023.5.14)
Carambola(AT91SAM9G25) the second version of hardware released and under test. Note: The first version failed for the wrong tuning of DDR lines. @ 2023.5.14Apricot(S3C2416) hardware final design finished with version/revisionv1r0x205, the software for this board is under development @ 2023.5.17Almond Mini(S3C2410) hardware final design finished with version/revisionv1r1x208@ 2023.5.20Carambolaturning into a stall state for the unclear DDR2 initialization procedures of atmel mpus. @ 2023.5.26Apricotpushed new hardware version v1r1, which fixed UDEV clock input line and added pad teardrops. @ 2023.5.27- added new plan for
Oxalis Mini@ 2023.5.27 - cut down project plan with existing working plan. @ 2023.5.28
Apricot(S3C2416) hardware debug is done, DDR2 initialization is ok. Starting USB 2.0 HS and Linux software debug. @ 2023.6.2- corrected
Apricotddr clock information in project progress chart to 133 MHz. @ 2023.6.2 - dropped
Carambola; startingOxalis Minischematic design. @ 2023.6.4 - revisioning
Carambola; startingHypericum. @ 2023.6.24 Hypericum(a alias ofOxalis Mini)(Allwinner-A20) first board test done, revisioning;Apricot(S3C2416) third board(v1r3) test done, revisioning;Carambolaboard under test. @ 2023.7.2- Fixed SDIO pull-up problem for
Hypericum,Carambola,Apricotboards. @ 2023.7.11 Carambolanewest board tested done; needed to roll back to version that did not pulled up at SDIO, SAM9G25 have internal pull-up for SDIO. @ 2023.7.15Carambola,Hypericumfixed with reset chip, SDIO pull-ups, ExtIO layout. These versions are verified and committed. @2023.7.22
- the version identifier on silkscreen of boards:
(1)v1r2e3means version 1, revision 2, edition 3.
typically written inversion 1.1.1.
(2)v1r2x202means version 1, revision 2, date May 14th.
typically written inversion 1.1, 5.14.
these types of version identifiers are all used among boards.