Skip to content
View johan92's full-sized avatar

Block or report johan92

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results

SDRAM controller for MIPSfpga+ system

Verilog 24 7 Updated Oct 30, 2020

Fun with malloc() and free(): PoC implementation, tracing, training deep neural networks

Jupyter Notebook 14 2 Updated May 26, 2017

SoC based on RISC V ISA

Verilog 10 3 Updated Apr 22, 2022

CHO is a benchmark suite for OpenCL FPGA Accelerators

C 19 11 Updated Jun 18, 2017

linux source code for de1 soc mtl touch screen

C 6 6 Updated Apr 8, 2014

Simple stack interpreter (forth-like)

C 1 1 Updated Aug 30, 2015

A Two-Way Active Measurement Protocol

C 72 41 Updated Sep 13, 2022

TCL based extensible Register File Generator

Tcl 4 1 Updated May 16, 2018

openHMC - an open source Hybrid Memory Cube Controller

SystemVerilog 50 14 Updated Apr 27, 2016

Verilog Ethernet components for FPGA implementation

Verilog 2,746 791 Updated Feb 27, 2025

Pattern searche based on Bloom algorithm.

SystemVerilog 8 2 Updated Jul 20, 2015

Testing FPGA2SDRAM interface on Altera Cyclone V SoC

C 14 5 Updated May 12, 2015