Stars
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
Network on Chip Implementation written in SytemVerilog
OpenTitan: Open source silicon root of trust
FPGA Controller for APA102 and compatible RGB LEDs
RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
All-digital FM Stereo Modulator described in Verilog.
Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)
Ted Fried's MicroCore Labs Projects - FPGA CPU cores and emulators for the 8088, 8086, 8051, 6502, 68000, Z80, Risc-V, and also Typewriter and EPROM Emulator projects. MCL51, MCL64, MCL65, MCL65+, …
IBM PC Compatible SoC for a commercially available FPGA board
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
Intel® Hardware Accelerated Execution Manager (Intel® HAXM)
32-bit RISC-V system on chip for iCE40 FPGAs
Random instruction generator for RISC-V processor verification
A directory of Western Digital’s RISC-V SweRV Cores
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
VHDL helper library with generic components and helper functions
Verilog+VHDL Hierarchy Management tool ( IDE ) wraps around Vim, runs in Linux terminal window.
RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni