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bytecode Public
An attempt to implement OCaml byte code as a system verilog module (behavioural and RTL versions)
OCaml UpdatedSep 23, 2026 -
xc7-bitstream-tools Public
Wrapper to build XC7 examples in nextpnr and post-process to bitstream/uf2
Python UpdatedSep 23, 2026 -
fasm2netlist Public
Extract an LVS setlist from an FPGA bitstream ready for simulation or Z3 formal comparison
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System-Verilog-suite Public
An attempt to convert dumps generated with verilator --json-only back to Verilog
OCaml UpdatedSep 23, 2026 -
buildroot Public
Forked from buildroot/buildrootBuildroot, making embedded Linux easy. Note that this is not the official repository, but only a mirror. The official Git repository is at https://gitlab.com/buildroot.org/buildroot/. Do not open i…
Makefile Other UpdatedSep 23, 2026 -
litex Public
Forked from enjoy-digital/litexBuild your hardware, easily! customised for sonata board
Python Other UpdatedSep 23, 2026 -
apio Public
Forked from FPGAwars/apio🌱 Open source ecosystem for open FPGA boards
Python GNU General Public License v3.0 UpdatedSep 23, 2026 -
nextpnr Public
Forked from openXC7/nextpnrnextpnr portable FPGA place and route tool
C++ ISC License UpdatedSep 22, 2026 -
prjxray-db Public
Forked from f4pga/prjxray-dbProject X-Ray Database: XC7 Series
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openFPGALoader Public
Forked from trabucayre/openFPGALoaderUniversal utility for programming FPGA
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apio-virtex7 Public
apio on Xilinx Virtex-7 (VC707) via nextpnr-himbaechel: setup, blinky, 1 GB LiteX Linux SoC
Verilog UpdatedSep 19, 2026 -
tools-openxc7 Public
Forked from FPGAwars/tools-openxc7Apio package with selected binaries from the openXC7 project
Python GNU General Public License v3.0 UpdatedSep 19, 2026 -
apio-definitions Public
Forked from FPGAwars/apio-definitionsapio resources
Python GNU General Public License v3.0 UpdatedSep 19, 2026 -
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sonata-linux Public
A RISCV based linux for sonata-system boards, optimised for 8M hyper ram and 32M serial flash
Makefile UpdatedSep 17, 2026 -
linux-on-litex-vexriscv Public
Forked from litex-hub/linux-on-litex-vexriscvLinux on LiteX-VexRiscv sonata linux patches
Python BSD 2-Clause "Simplified" License UpdatedSep 17, 2026 -
litex-boards Public
Forked from litex-hub/litex-boardsLiteX boards files for sonata
Python BSD 2-Clause "Simplified" License UpdatedSep 17, 2026 -
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vc707-openflow-demos Public archive
Three Virtex-7 VC707 demos built by a fully open toolchain: yosys/SVS -> place_lef -> nextpnr-xilinx -> prjxray. No Vivado at any stage.
Verilog ISC License UpdatedSep 8, 2026 -
liteeth Public
Forked from enjoy-digital/liteethSmall footprint and configurable Ethernet core
Python Other UpdatedSep 3, 2026 -
ibex-demo-system Public
Forked from lowRISC/ibex-demo-systemA demo system for Ibex including debug support and some peripherals
C Apache License 2.0 UpdatedAug 19, 2026 -
json_drc-portable Public
utilities fro converting between System-Verilog-suite and vivado using rapidwright
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vcdparser Public
Forked from jrrk/vcdparservcd parser written in OCaml, adapted from the Python version by Eric Anderson
OCaml GNU General Public License v3.0 UpdatedJul 23, 2026 -
nextpnr-xilinx Public
Forked from openXC7/nextpnr-xilinxExperimental flows using nextpnr for Xilinx devices
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prjxray Public
Forked from f4pga/prjxrayDocumenting the Xilinx 7-series bit-stream format.
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OriginMonitor Public
Provides a Qt App (for macOS initially) that displays the status of your Celestron Origin telescope
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PCLDev Public
PixInsight Class Library extension module development (especially for Celestron Origin)
C++ UpdatedJun 20, 2026 -
OpenROAD-flow-scripts Public
Forked from The-OpenROAD-Project/OpenROAD-flow-scriptsOpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
Verilog Other UpdatedJun 20, 2026
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