给非 EDA 领域人进入该行业的一些资料。
| Name | Category | Level | Author Org | YEAR-Paper | Link | Recommend | Notes |
|---|---|---|---|---|---|---|---|
| CVDP | RTL generation | NVIDIA | - | github, huggingface | - | ||
| RTLLM | RTL generation | single module | HKUST | RTLLM | github | - | |
| AssertLLM | RTL Assertion generation | single module | HKUST | AssertLLM | github | - | |
| RTL-Coder | RTL generation | HKUST | RTLCoder | github | - | ||
| RTLBench | RTL generation | NUDT | RTLBench | github | - | ||
| RealBench | RTL generation | ICT,CAS | RealBench | github | - | ||
| RTL-OPT | RTL Code Optimization | HKUST | RTL-OPT | anonymous github | - | ||
| verilog-eval | RTL generation | single module | NVIDIA | VerilogEval, Revisiting VerilogEval | NVlabs/verilog-eval | ⭐ | - |
| RTL-Repo | RTL complement | AUC | 2024.5-RTL-Repo | github, huggingface | - | ||
| MEIC | RTL Debug | single module | SEU | 2025.5-MEIC-[ICCAD] | SEU-ACAL/reproduce-MEIC-ICCAD-24 | - | |
| GenBen | RTL generation | - | 2024.9-GenBen-[OpenReview] | github | - | ||
| UVLLM | RTL Debug | singl module | SEU | 2024.10-UVLLM-[DAC] | amyuch/UVLLM | - | |
| ChipBench | generate;debug;ref model | single module;multi module;cpu | - | 2026.2-ChipBench | github | a full flow framework，several data inside | |
| AssertSolver | RTL Debug assertion | single module | SEU | 2025.3-AssertSolver-[DAC] | github | ⭐ | - |
| HWE-Bench | debug | PKU | 2026.4-HWE_Bench-[] | ||||
| ChipVerilog | RTL generatation | ip/core | HKUST | 2026.7-ChipVerilog | - |
| Name | Category | Author Org | Paper | Link | Notes |
|---|
部分借助gpt整理
| Name | Type | 语言支持 | 特点 | 性能 |
|---|---|---|---|---|
| Verilator | 编译型仿真 | Verilog/SystemVerilog子集 | 转C++高速仿真 | ★★★★★ |
| Icarus Verilog | 解释型仿真 | Verilog | 轻量级 | ★★☆☆☆ |
| GHDL | VHDL仿真 | VHDL | 与Yosys结合支持综合 | ★★★☆☆ |
| GTKWave | 波形查看 | VCD/FST | Debug波形可视化 | ★★★★☆ |
| Cocotb | Python验证框架 | Verilog/VHDL | Python驱动仿真 | ★★★★☆ |
| 工具 | 类型 | 功能 | 适用场景 |
|---|---|---|---|
| SymbiYosys | Formal验证 | BMC/SMT | 小模块形式验证 |
| Yosys-SMTBMC | SMT求解 | 有界模型检测 | Assertion验证 |
| JasperGold (商业) | 工业Formal | 完整Property验证 | 工业级验证 |
| OneSpin (商业) | Formal | RTL属性验证 | 高端芯片验证 |
| XLS (开源) (not an officially supported Google product) | IR(中间件语言)(dslx语言写硬件代码->可转rtl) | Accelerated HW Synthesis | x |
| pyslang | SystemVerilog解析器 | SystemVerilog解析器 | 代码分析、工具开发 |
| pyuvm | UVM仿真框架 | Python实现的UVM | Python驱动仿真 |
VCD_ANALYZER | 纯为本vcd波形查询工具 for llm
circt | IR(中间件语言) 一个整顿工具链的项目
TraceWeave | 波形分析的mcp.咋搞这么复杂
circuit-tracer | 模型找电路图，不知道找啥
为了纯开源仿真工具使用UVM，使用verilator支持的uvm
Opensource is future
Great CHIPS Alliance! chisel原来也是他们的