Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

RISC-V CPU Core (RV32IM)

一步一步写MIPS CPU

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

An FPGA-based full-stack in-storage computing system.

A Homework for Computer Architecture at SJTU

A simple MIPS CPU for BUAA CO course (and now NSCSCC).

ACM Class 2017 Computer Architecture

FPGA design repository