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5 stars written in Verilog
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SERV - The SErial RISC-V CPU

Verilog 1,711 240 Updated Dec 16, 2025

A Verilog HDL model of the MOS 6502 CPU

Verilog 363 100 Updated Apr 8, 2023

FuseSoC-based SoC for VeeR EH1 and EL2

Verilog 335 74 Updated Dec 11, 2024

The source code to the Voss II Hardware Verification Suite

Verilog 56 13 Updated Nov 28, 2025
Verilog 32 11 Updated Jul 9, 2022