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Lists (16)

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Starred repositories

9 results for source starred repositories written in Verilog
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ultraembedded / riscv

RISC-V CPU Core (RV32IM)

Verilog 1,558 271 Updated Sep 18, 2021

nukeykt / Nuked-MD-FPGA

Mega Drive/Genesis core written in Verilog

Verilog 311 13 Updated Oct 20, 2024

MIPSfpga / schoolMIPS

CPU microarchitecture, step by step

Verilog 203 64 Updated Nov 1, 2020

manish-kj / PACoGen

PACoGen: Posit Arithmetic Core Generator

Verilog 75 16 Updated Aug 16, 2019

mattvenn / wokwi-verilog-gds-test

Verilog 55 20 Updated Oct 24, 2022

TinyTapeout / tinytapeout-mpw7

TinyTapeout-01 submission repo

Verilog 32 7 Updated Nov 28, 2022

bzeeno / riscv-cpu

Pipelined RISC-V CPU

Verilog 23 1 Updated Jun 9, 2021

ChenJianyunp / Posit32-2-exact-multiply-accumulator

This is a hardware implementation of exact multiply accumulator for 32-bit posit number with es=2

Verilog 17 4 Updated Jan 27, 2018

mattvenn / wokwi_filler

Verilog 1 Updated Sep 22, 2022

Starred topics