PicoRV32 - A Size-Optimized RISC-V CPU

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Must-have verilog systemverilog modules

SERV - The SErial RISC-V CPU

A small, light weight, RISC CPU soft core

MNT VA2000, an Open Source Amiga 2/3/4000 Graphics Card (Zorro II/III), written in Verilog

RISC-V XV6/Linux SoC, marchID: 0x2b

Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.

synthesiseable ieee 754 floating point library in verilog

RISC-V Formal Verification Framework

Repository for basic (and not so basic) Verilog blocks with high re-use potential

mor1kx - an OpenRISC 1000 processor IP core

VRoom! RISC-V CPU

iCESugar FPGA Board (base on iCE40UP5k)

An open source SPI flash emulator and monitor

🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board

A simple, basic, formally verified UART controller

Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation

A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals

Minimax: a Compressed-First, Microcoded RISC-V CPU

CPU microarchitecture, step by step

🌱 ❄️ Collection of open-source peripherals in Verilog

Compact FPGA game console

Universal Memory Interface (UMI)

IceChips is a library of all common discrete logic devices in Verilog

Various caches written in Verilog-HDL

Regression test suite for Icarus Verilog. (OBSOLETE)

Public examples of ICE40 HX8K examples using Icestorm