VUnit is a unit testing framework for VHDL/SystemVerilog

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

GPL v3 2D/3D graphics engine in verilog

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improv…

Z80 CPU and Memory Module

IEEE 754 single precision floating point library in systemverilog and vhdl

Hardware/Software Co-design environment of a processor core for deterministic real time systems

core files for the MiST fpga

FPU Double VHDL

Experimental CPU with software-defined instruction set.

Convergent Tech Monochrome NGEN to VGA FPGA Converter V2.00