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rv3n Public
RV3N--- a RV32IMC processor core, which has a new pipeline with "3+N" stages.
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This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your F…
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SuperScalar-RISCV-CPU Public
SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
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rv32m-multiplier-and-divider Public
a multiplier÷r verilog RTL file for RV32M instructions
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riscv-cores-list Public
Forked from riscvarchive/riscv-cores-listRISC-V Cores, SoC platforms and SoCs
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R8051 Public
8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.
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verilog-divider Public
a super-simple pipelined verilog divider. flexible to define stages
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