PicoRV32 - A Size-Optimized RISC-V CPU

Verilog Ethernet components for FPGA implementation

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

RTL, Cmodel, and testbench for NVDLA

IC design and development should be faster，simpler and more reliable

SERV - The SErial RISC-V CPU

RISC-V CPU Core (RV32IM)

Verilog PCI express components

A small, light weight, RISC CPU soft core

Verilog library for ASIC and FPGA designers

OpenXuantie - OpenC910 Core

32-bit Superscalar RISC-V CPU

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

OpenXuantie - OpenC906 Core

Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

An attempt to recreate the RP2040 PIO in an FPGA

Silicon-validated SoC implementation of the PicoSoc/PicoRV32

High throughput JPEG decoder in Verilog for FPGA

通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器

OpenXuantie - OpenE902 Core

OpenXuantie - OpenE906 Core

PCIE 5.0 Graduation project (Verification Team)

A fully-integrated FT8 protocol receiver on 130nm CMOS

A series of (practise) projects of RISC-V cores. All cores will support at least the I instruction set. Expect bugs/limitations for earlier ones

An attempt to recreate the RP2040 PIO in an FPGA

TinyTapeout Mini AI-Engine: a 2x2 Coarse-Grained Reconfigurable Array with NoC