A Python package to use FPGA development tools programmatically.

Document describing different gotchas in Intel Quartus SystemVerilog code synthesis.

SystemVerilog RTL Linter for YoSys

Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and multi cycle instructions, ALU unit works in parallel with a mult…

An open-source HDL register code generator fast enough to run in real time.

SystemVerilog Tutorial

UVM based Verification of SPI_Protocol. A Serial intra System Communication Peripheral Protocol.

Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

GPL v3 2D/3D graphics engine in verilog

Python bindings for slang, a library for compiling SystemVerilog

Python library for parsing module definitions and instantiations from SystemVerilog files

Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

Communication framework for RTL simulation and emulation.

FPGA exercise for beginners

UVM style testbench for the CODMA project, used to strengthen my knowledge and skills in UVM. This project is a work in progress.

USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL

An opinionated build environment for EDA projects

APB UVC ported to Verilator

Advanced Encryption Standard (AES-128bits)

A keep it simple (and stupid) version of RISC-V implementation in RTL and simulation using Verilator

Fully differential sample and hold circuit

Spicing up your UVM driver: noise injection made easy with callback iterators

High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

MathLib DAC 2023 version

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

SystemVerilog Linter based on pyslang

Open source FPGA-based NIC and platform for in-network compute