IC design and development should be faster，simpler and more reliable

The Ultra-Low Power RISC-V Core

RISC-V CPU Core (RV32IM)

Verilog library for ASIC and FPGA designers

An open source GPU based off of the AMD Southern Islands ISA.

32-bit Superscalar RISC-V CPU

Various HDL (Verilog) IP Cores

synthesiseable ieee 754 floating point library in verilog

mor1kx - an OpenRISC 1000 processor IP core

A DDR3 memory controller in Verilog for various FPGAs

Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.githu…

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

A simple, basic, formally verified UART controller

This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调试器。

This repository hosts the code for an FPGA based accelerator for convolutional neural networks

Simple 8-bit UART realization on Verilog HDL.

FPGA based transmitter

Human Resource Machine - CPU Design #HRM