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Achievements

Achievement: Pair ExtraordinaireAchievement: YOLOAchievement: Pull Sharkx2Achievement: Starstruck

Achievements

Achievement: Pair ExtraordinaireAchievement: YOLOAchievement: Pull Sharkx2Achievement: Starstruck

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@ml-explore
ml-explore ml-explore
Machine learning research on your laptop or in a data center - by Apple
@AlbertaBeef
Mario Bergeron AlbertaBeef
Just a guy learning about AI

Quebec, Canada

@pulp-platform
pulp-platform
@ECE382M-20-Fa23
ECE382M.20: System-on-Chip Design, Fall 2023 ECE382M-20-Fa23
@songhan
Song songhan
Song Han is an associate professor at MIT EECS and distinguished scientist at NVIDIA. His research interest is efficient AI computing.

MIT, NVIDIA

@Silabs-ArjanB
Arjan Bink Silabs-ArjanB

Silicon Laboratories Oslo

@SiliconLabs
Silicon Labs SiliconLabs
Silicon Labs is a leading provider of solutions for a smarter, more connected world. The official GitHub account contains officially supported repositories.

Austin, TX

@cathalmccabe
Cathal McCabe cathalmccabe
AMD Xilinx University Program

Dublin, Ireland

@MikeOpenHWGroup
Mike Thompson MikeOpenHWGroup
Functional verification of RTL for ASICs and FPGAs. Sole Proprietor at Covrado and Director of Engineering, Verification Task Group at the OpenHW Foundation.

@openhwgroup Ottawa, Ontario, Canada

@torvalds
Linus Torvalds torvalds

Linux Foundation Portland, OR

@hdl
Hardware Description Languages hdl
@strichmo
Steve Richmond strichmo
Design Verification Manager Central R&D

Silicon Labs Austin TX

@hpsresearchgroup
hpsresearchgroup
@UT-LCA
Laboratory for Computer Architecture UT-LCA
Any public works done by LCA here
@silabs-hfegran
Henrik Fegran silabs-hfegran
Verification Manager @SiliconLabs

Silicon Laboratories Inc. Oslo, Norway

@os-fpga
The Open-Source FPGA Foundation os-fpga
@SymbiFlow
SymbiFlow SymbiFlow
Open source flow for generating bitstreams from Verilog.

The Internet

@ganeshgore
Ganesh Gore ganeshgore

@QuickLogic-Corp Salt Lake City, Utah

@riscv
RISC-V riscv
The Open-Standard Instruction Set Architecture

Zurich, CH

@ZipCPU
Dan Gisselquist ZipCPU

Gisselquist Technology, LLC

@olofk
Olof Kindgren olofk
@sangwoojun
Sang-Woo Jun sangwoojun
@aignacio
Anderson Ignacio aignacio
@xupgit
Xilinx University Program xupgit

Xilinx San Jose, CA, USA

@blakeblackshear
Blake Blackshear blakeblackshear

@concertgenetics Nashville, TN

@neelgala
Neel Gala neelgala

InCore Semiconductors Pvt. Ltd Chennai,India

@zhenman
Zhenman Fang zhenman

SFU Burnaby, BC, Canada

@vipinkmenon
Vipin K vipinkmenon

Birla Institute of Technology and Schience Goa, India

@alexforencich
Alex Forencich alexforencich

UC San Diego La Jolla, CA

@drom
Aliaksei Chapyzhenka drom
always @ posedge

@sifive Terra ⴲ

@doonny
Dong Wang doonny
Prof. at The Heterogeneous Computing Lab of Beijing Jiaotong University

Beijing Jiaotong University Beijing, China

@BalaDhinesh
Dhinesh BalaDhinesh
IIT Madras Electrical Engineering Electronics and VLSI Enthusiast || GSoC'21 @ FOSSi Foundation

Indian Institute of Technology Madras Chennai

@fpgadeveloper
Jeff Johnson fpgadeveloper

Opsero Electronic Design Inc. Quebec City

@kelvinxu
Kelvin Xu kelvinxu

UC Berkeley Toronto, Canada

@palmer-dabbelt
Palmer Dabbelt palmer-dabbelt

Rivos Redwood City, CA

@davidbiancolin
David Biancolin davidbiancolin
Engineer @sifive; U of T + Cal Alum

@sifive Berkeley

@yunsup
Yunsup Lee yunsup
@kasanovic
Krste Asanovic kasanovic

UC Berkeley, SiFive

@aswaterman
Andrew Waterman aswaterman
SiFive co-founder, RISC-V architect, BSE Duke, Ph.D. Cal

@sifive @riscv Berkeley, CA, USA

@semidynamics-dev
Semidynamics semidynamics-dev
European provider of the finest RISC-V Cores and Vector Units

Semidynamics Technology Services Barcelona

@mkkassem
Mohamed Kassem mkkassem

efabless.com The Universe

@thoughtpolice
Austin Seipp thoughtpolice
i live 400 miles underground

East River Source Control Austin, TX

@vaughnbetz
vaughnbetz
@seldridge
Schuyler Eldridge seldridge
Hardware compiler hacker. Sometimes RISC-V accelerator builder. PhD from @bu-icsg.

@SiFive New York, NY

@JananiRamjee
Janani Ramjee JananiRamjee
I code, mostly for open source hardware/software. Ex- SHAKTI Intern
@rsnikhil
Rishiyur S. Nikhil rsnikhil
Hardware design: mostly RISC-V, mostly using Bluespec BSV. Also Haskell, RISC-V Formal Specifications, tutorials.

Bluespec, Inc. Framingham, MA, USA

@Ravenwater
Theodore Omtzigt Ravenwater
Computer Architect and custom compute engine developer for robotics, computer vision, and high-performance computing applications.

Stillwater Supercomputing, Inc. Freeport, Maine

@shivanishah269
Shivani Shah shivanishah269

IIITB Bangalore

@nickson-jose
nickson-jose
Physical Design, VLSI.

India

@mattvenn
Matt Venn mattvenn
Engineer and Science Communication. On a mission to make ASICs more accessible. YosysHQ & Tiny Tapeout founder member.

@YosysHQ-GmbH @TinyTapeout Valencia, Spain