XLS: Accelerated HW Synthesis

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

SERV - The SErial RISC-V CPU

Advanced Interface Bus (AIB) die-to-die hardware open source

Vitis In-Depth Tutorials

RTL, Cmodel, and testbench for NVDLA

Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow

Random instruction generator for RISC-V processor verification

贵校课程资料民间整理

FAIR's research platform for object detection research, implementing popular algorithms like Mask R-CNN and RetinaNet.

collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning

CNN acceleration on virtex-7 FPGA with verilog HDL

verilog CNN generator for FPGA

NetFPGA public repository

A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the fut…

Tensorflow prebuilt binary for Windows

💿 Free software that works great, and also happens to be open-source Python.

PicoRV32 - A Size-Optimized RISC-V CPU

Verilog Ethernet components for FPGA implementation

NVDLA SW

A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz

Hardware implementation of the SHA-256 cryptographic hash function

A FPGA friendly 32 bit RISC-V CPU implementation

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit