A USB 2.0 PHY on the sky130 open PDK, designed by AI agents driving klayout-tools and the open-source flow — cocotb + Icarus and Yosys/OpenROAD on the digital side, xschem + ngspice on the analog side.
Status: digital UTMI-side RTL in progress. The full-speed receive and transmit paths (bit sync, NRZI encode/decode, (de)stuffing, framing, UTMI CDC) are implemented and verified under cocotb; the analog front end and layout do not exist yet. See the scope note below for what is deliberately not being built yet.
Built agent-native. Every specification, decision record, testbench, and line of documentation in this repo is produced by AI agents working from a ratified spec and an append-only evidence trail — not human-authored work that agents merely assisted with. Verification is the product: every claim traces to a recorded result. Where the agents hit friction with the open-source tooling — most often klayout-tools — that friction gets filed as a public issue against the tool itself, so the fix benefits everyone using sky130, not just this repo.
A USB 2.0 PHY is an assembly — a PLL-based clock/data recovery path, current-mode drivers, differential receivers, squelch envelope detection, and a digital UTMI layer. Most of those analog pieces are being designed as their own canary blocks in sibling repos and do not exist in finished form yet.
So this repo starts with the half that does not depend on them:
- In scope now — the target specification, the block-level architecture and partitioning, and the digital UTMI side (RTL, verification, synthesis).
- Not in scope yet — the analog assembly. It waits on the sibling blocks that supply the PLL, drivers, and receivers.
Full-speed (12 Mbps) is the first functional target; high-speed (480 Mbps) is a stretch goal, not a commitment.
The specification has been frozen since 2000, which makes it an unusually stable target for a multi-month agent-driven design. HS PHYs have been fabricated and verified at 0.25 µm and 0.35 µm — nodes coarser than sky130 — so feasibility at this node is not the open question. And the only open-source sky130 attempt we are aware of (Vlsir/Usb2Phy) built the analog half and went dormant in February 2023.
It is also the hardest workout in the program for the tools themselves, which is the canary's actual job: a block that spans digital synthesis, analog design, and the seam between them exercises paths no single-domain block reaches.
Ratified 2026-08-05 — see spec/usb2-phy.md for the
full specification: signaling/speed target, UTMI interface, reference clock
and PLL jitter budget, supply architecture, analog sub-block interface
requirements, verification scope, and the decision log behind each of those.
spec/architecture.md has the block diagram and
build-here/sibling-canary partition table.
Maturity ladder: spec ratified → UTMI RTL verified → analog blocks available → assembly → DRC/LVS-clean → shuttle seat → measured silicon. Current position: spec ratified, FS receive/transmit RTL implemented and cocotb-verified; the physical flow (synthesis/P&R/STA/LVS/DRC) has been run only for the toolchain-plumbing stub, never for the real UTMI RTL.
docs/characterization.md is the authoritative
characterization summary: every row of spec/usb2-phy.md §6 indexed against
the evidence records that exist, per PVT corner, with the record id behind
each entry. Its headline today is that zero spec rows have design-anchored
evidence — the committed records are the smoke-utmi_stub toolchain
experiment (design.anchors_design_claim: false), not the real datapath.
spec/ ratified spec + decision records
rtl/ UTMI-side Verilog sources
verification/ cocotb testbenches
flow/ synthesis + P&R recipes (Yosys, OpenROAD), driven through klt
design/ analog schematics (empty until the sibling blocks land)
sim/ analog testbenches + PVT corner results (empty for now)
layout/ GDS + DRC/LVS reports (klayout-tools driven)
measurements/ silicon characterization (empty until tape-out)
.github/workflows/ci.yml runs npm run check:ci on every pull request and push to main, bootstrapping Icarus
Verilog, klt, and cocotb so both the pytest and cocotb/RTL layers of the
verification suite actually run — see
verification/README.md
for exactly what is (and, on purpose, is not) exercised in CI.
Apache License 2.0 — see LICENSE.