PicoRV32 - A Size-Optimized RISC-V CPU

32-bit Superscalar RISC-V CPU

Project Apicula 🐝: bitstream documentation for Gowin FPGAs

An attempt to recreate the RP2040 PIO in an FPGA

i8080 precise replica in Verilog, based on reverse engineering of real die

SoC design for Milkymist One - LM32, DDR SDRAM, 2D TMU, PFPU

This repository contains small example designs that can be used with the open source icestorm flow.

Introductory course into static timing analysis (STA).

Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC

PACoGen: Posit Arithmetic Core Generator

Demo projects for various Kintex FPGA boards

A look ahead, round-robing parametrized arbiter written in Verilog.

FPGA USB 1.1 Low-Speed Implementation

TinyTapeout-01 submission repo

A design for TinyTapeout

Is a collection of NULL Convention Logic (NCL) circuits and libraries written in Verilog to provide the experience of logically determined design in a familiar context. The tools used are Icarus ve…

Submission template for Tiny Tapeout 9 - Verilog HDL Projects

Mini RISC-V SOC

Side channel communication test within an FPGA

porting lowRISC to yosys/nextpnr/trellis on the Lattice ECP5 fpga

VGA Clock Design For Tiny Tapeout 05

1024x8 SRAM test for Tiny Tapeout on IHP shuttle