verilator

Here are 7 public repositories matching this topic...

wyvernSemi / pcievhost

PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities

c verification verilog virtual vivado modelling icarus-verilog ghdl cosim pcie pli bfm verilator nvc xsim questa-sim

Updated Jun 16, 2026
C

xThaid / fpga-lb

Star

A toy L4 load balancer running on FPGA

networking fpga ocaml load-balancer riscv freertos dataflow verilator quartus vexriscv hardcaml

Updated Feb 28, 2022
C

hsnaves / gigatron

Star

Verilog model and simulator (emulator) for the Gigatron TTL microcomputer .

emulator verilog verilator gigatron

Updated Mar 26, 2021
C

soct-org / SoCeteer

Star

SoCeteer - A framework for designing and running RISC-V-based SoCs on FPGA and in Simulation, built on top of Chisel.

chisel risc-v xilinx-vivado verilator soc-design

Updated Aug 10, 2026
C

fredrequin / verilator_helpers

Star

C++ objects to help verilator simulations

cpp riscv uart m68k simulation-model verilator lm32 sdram

Updated Feb 17, 2026
C

dlwotjr / ibex-pqc-experiments

Star

Ibex RV32 custom-instruction integration and PQC bare-metal porting experiments with Verilator

riscv systemverilog post-quantum-cryptography bare-metal fusesoc verilator ibex custom-instructions

Updated Sep 7, 2026
C

Development of a minimal RISC-V System on Chip and integration with a computational accelerator written in Verilog. It serves as an example of a minimal architecture and as a foundation for future expansions (real hardware accelerators for scientific computing and AI).

c verilog computer-architecture risc-v system-on-chip verilator litex migen riscv-asm bare-metal-programming system-on-chip-design

Updated May 17, 2026
C

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verilator

Here are 7 public repositories matching this topic...

wyvernSemi / pcievhost

xThaid / fpga-lb

hsnaves / gigatron

soct-org / SoCeteer

fredrequin / verilator_helpers

dlwotjr / ibex-pqc-experiments

AlexanderGSC / Mini-Soc-Acc

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