Digital Design laboratory project demonstrating binary arithmetic circuits, including Half Adder, Full Adder, Half Subtractor, Full Subtractor, with interactive NI Multisim simulations, truth tables, and logical equation analysis (Logic Design, UNIWA).

This repository focuses on designing and simulating logical circuits using Verilog HDL (Hardware Description Language) with the Icarus Verilog simulator.

Repository containing digital circuit projects developed for the INF01058 course at UFRGS.

Verilog code for combinational and sequential circuits

Digital System Design Verilog Implementation

Useful VHDL scripts for hardware description.

Optimized 32-Bit Full Adder, CEC-SAT Verifier & 2-SAT Solver

A digital design for a carry select adder

Different adders code in VHDL and Comparison

This repository contains project done in LabView IDE from Basic Gates designing, Adders, Counters, Encoders, Decoders and Examples to connect to external Arduino like embedded systems

A Diode-Transistor-Logic Adder System built from Scratch, with simplicity and robustness in mind

Tree adder for fast addition

Progetti di Elettronica Digitale 2021.

design and tb for 32-bit kogge stone adder

Circuits of combinational elements

В данном репозитории будет рассказано о 32-битном сумматоре с последовательным переносом.

In this project, I conducted an in-depth comparative analysis of various adder architectures to assess their performance in terms of delay and power consumption.