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multiplier

Here are 99 public repositories matching this topic...

zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the fun…

cpu processor simd verilog alu adder instruction-set-architecture cadence-virtuoso multiplier verilog-project processor-design

Updated Jul 17, 2022
Verilog

antonblanchard / vlsiffra

Create fast and efficient standard cell based adders, multipliers and multiply-adders.

verilog booth vlsi adder multiplier physical-design dadda amaranth-hdl

Updated Sep 20, 2023
Python

suoglu / Fixed-Floating-Point-Adder-Multiplier

16-bit Adder Multiplier hardware on Digilent Basys 3

fpga hardware verilog vivado fixed-point floating-point adder multiplier binary16

Updated Aug 3, 2023
Verilog

greenelab / multi-plier

An unsupervised transfer learning approach for rare disease transcriptomics

machine-learning analysis dataset methodology bioinformatics-analysis gene-expression-signatures multiplier plier rare-diseases

Updated Jan 27, 2020
HTML

tharunchitipolu / Dadda-Multiplier-using-CSA

Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.

rtl verilog fulladder vlsi multiplier hardware-description-language wallace vlsi-design vlsi-project dadda-tree carry-save-adder fast-multiplication dadda-multiplier tree-multipliers

Updated Jun 6, 2024
Verilog

scale-lab / DRUM

The Verilog source code for DRUM approximate multiplier.

verilog logic-synthesis multiplier approximate-computing approximate-circuits

Updated May 4, 2023
Verilog

RaulMurillo / Flo-Posit

Posit Arithmetic Cores generated with FloPoCo

vhdl adder posit unum multiplier posit-arithmetic flopoco

Updated May 8, 2026
VHDL

Essenceia / BFloat16

RTL implementation of a performance/area optimized bfloat16 adder and multiplication.

asic verilog floating-point adder multiplier bfloat16 bf16

Updated Mar 28, 2026
Verilog

contributte / forms-multiplier

🔁 Form multiplier & replicator for Nette Framework

forms nette replicator multiplier contributte

Updated Mar 29, 2026
PHP

rcetin / booth_wallace_multiplier

Booth encoded Wallace tree multiplier

fpga verilog multiplier booth-wallace

Updated May 24, 2018
Verilog

mnb27 / Fast-Multipliers

32-bit Wallace and Dadda Tree Multiplier

verilog multiplier

Updated Jun 26, 2020
Verilog

tharunchitipolu / Multi-operations-toolbox-with-baugh-wooley-multiplier

Given A and B are 64-bit inputs. With two selection lines s1 and s0 to perform the operations, A+B, A-B, AB, C+AB using Baugh Wooley multiplier

digital verilog vlsi verilog-hdl multiplier hardware-description-language vlsi-circuits baugh-wooley digitalelectronics

Updated Jun 1, 2021
Verilog

Saadia-Hassan / 8x8Multiplier-Using-Vedic-Mathematics

An 8-bit multiplier is synthesized and simulated in Xilinx ISE using Verilog HDL. The multiplication is performed using Vedic Mathematics which is proved to consume less power and faster than conventional multipliers.

simulation synthesis verilog-hdl xilinx-ise multiplier adders vedic-mathematics

Updated Jul 27, 2020
Verilog

gagan405 / WallTree

A VHDL code generator for wallace tree multiplier

hardware vhdl wallace-tree-multiplier multiplier

Updated Apr 15, 2020
VHDL

Hassan313 / Approximate-Multiplier

This repository contains approximate 8-bit multiplier Verilog code.

verilog low-power multiplier approximate-computing runtime-configuration

Updated Jun 17, 2020
Verilog

suoglu / Carry-Save-Multiplier

Parameterized and 4-bit carry save multiplier design

fpga hardware verilog multiplier multipliers

Updated May 22, 2021
Verilog

pub-calculator-io / lcm-calculator

Free WordPress Plugin: Easily find the Least Common Multiple (LCM) of two or more numbers. Get step-by-step solutions using prime factorization, division, GCF, and Venn diagrams. www.calculator.io/lcm-calculator/

plugin wordpress wordpress-plugin calculator lcm multiplier online-calculator lcm-calculator calculator-plugin least-common-multiplier-calculator leastcommonmultiplier least-common-multiplier

Updated Jun 3, 2026
JavaScript

SDibla / VHDL-Booth_Multiplier

Booth's algorithm is a procedure for the multiplication of two signed binary numbers in two's complement notation. This code is a structural\behavioral implementation of the N bit Booth's multiplier in VHDL.

vhdl multiplier booth-algorithm

Updated May 19, 2021
VHDL

jpsimas / mbe-dadda-vhdl

Generator for unsigned n-bit modified Booth encoding Dadda tree multiplier code in VHDL written in C++. Based on https://github.com/HSOgawa/fast-multipliers/.

tree cpp vhdl booth modified multiplier mbe dadda

Updated Dec 24, 2019
C++

gustavohb / booth-multiplier

VHDL implementation of the Booth's multiplication algorithm

algorithm vhdl booth multiplier booths-algorithm booth-algorithm

Updated Aug 31, 2019
VHDL

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