vlsi-project

This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details

Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.

Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.

This repo contains a collection of Verilog+System Verilog+RTL+UVM+Protocols Projects

A simple tool to demonstrate the physical design steps of VLSI Design Flow.

This project is based on Digital VLSI Testing and Testability. The netlist is given as input, the code performs Dominance fault collapsing, Parallel fault simulation, Deductive fault simulation.

This project is based on Digital VLSI Testing and Testability. The netlist is given as input, the code performs SCOAP Controllability and Observability of circuit..

I've delved into leveraging my academic prowess to drive projects that contribute to my career advancement.

SHA-2 (Secure Hash Algorithm 2), of which SHA-256 is a part, is one of the most popular hashing algorithms out there.

Very Large Scale Integration project for CDMO class at @unibo

A curated collection of study resources, previous year papers, notes, assignments, labs, and projects for IIIT Delhi students.

Very Large Scale Integration solved using Costraint Programming and Minizinc

Synchronous FIFO

Digital Alarm Clock in Verilog HDL | FSM | ModelSim | Intel Quartus Prime | FPGA RTL Design

Digital Stopwatch – VHDL FPGA Implementation Technologies: VHDL, Xilinx ISE, FPGA, 7-Segment Display • Designed a fully functional VHDL digital stopwatch on FPGA with counter, control (start/stop/reset), and 7-segment display modules, demonstrating mastery of hardware description languages and FPGA synthesis workflows.

Verilog-based UART TX/RX design with FIFO buffering and RTL communication architecture.

Parameterized asynchronous FIFO in Verilog using Gray-coded pointers and 2-stage synchronizers for reliable clock domain crossing, with Full, Empty, Almost-Full and Almost-Empty flags.

Transistor-level 8-bit ALU design in Cadence Virtuoso — full schematic, layout, and timing optimization.

Verilog implementation of AMBA AHB Master and Slave with FSM control, FIFO integration, burst transfer (INCR4), and waveform-based protocol verification.