A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

Asynchronous FIFO for transferring data between two asynchronous clock domains

FIFO implementation with different clock domains for read and write.

Final project for the class "Application Specific Integrated Circuit Development"

Utilities for clock-domain crossing with an FPGA

In digital design, it is sometimes necessary to transfer data from one clock domain to another. However because of the nature of how data is stored, there is a probability the transaction will have a setup and hold violation or data is lost because of the different between the domain speeds.

A Fault Tolerant Globally-Asynchronous-Locally-Synchronous Inter-Chip Communication Bridge on FPGAs

This GitHub repository explores the concept of clock domain crossing using different techniques. The deliverable is not some hardware but rather an educational source for such techniques. Often used in verification, physical layout, and is a backbone to many concepts like PCIe or HDMI.

RTL designs and simulations for FIFO buffers (Synchronous & Asynchronous) in Verilog, targeting robust data handling architectures.

Production-ready asynchronous FIFO buffer with independent read/write clock domains for safe CDC operations. Features Gray code pointers, dual flip-flop synchronizers, metastability prevention, and parameterized design. Essential for SoC inter-module communication and multi-clock systems.