clock-domain-crossing

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Final project for the class "Application Specific Integrated Circuit Development"

Utilities for clock-domain crossing with an FPGA

Parameterizable Asynchronous FIFO with Gray Code Synchronization - A robust clock domain crossing solution in SystemVerilog

asic fpga verilog systemverilog fifo digital-design gray-code clock-domain-crossing asynchronous-fifo rtl-design

A basic SPI Slave implementation for Artix-7 FPGA (Basys 3) driven by an ESP32. Features a custom ALU with MAC support and proper CDC synchronization

fpga esp32 systemverilog basys3 spi-slave clock-domain-crossing

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